554   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
560   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
587   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
643   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
652   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
693   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
824   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
827   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
877   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
903   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
906   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
956   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
982   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
985   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1035   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1061   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1064   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1114   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1141   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1144   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1175   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1202   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1205   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1235   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1258   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1266   MODIFY_REG(TIMx->CCER,  in IC1Config()
1291   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1299   MODIFY_REG(TIMx->CCER,  in IC2Config()
1324   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1332   MODIFY_REG(TIMx->CCER,  in IC3Config()
1357   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1365   MODIFY_REG(TIMx->CCER,  in IC4Config()