Lines Matching refs:Timing
330 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
336 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
337 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
338 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
339 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
340 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
341 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
342 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
347 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
348 (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
349 (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | in FMC_NORSRAM_Timing_Init()
350 (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | in FMC_NORSRAM_Timing_Init()
351 ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | in FMC_NORSRAM_Timing_Init()
352 ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | in FMC_NORSRAM_Timing_Init()
353 Timing->AccessMode; in FMC_NORSRAM_Timing_Init()
359 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
379 … const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, in FMC_NORSRAM_Extended_Timing_Init() argument
390 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
391 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Extended_Timing_Init()
392 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
394 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Extended_Timing_Init()
396 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Extended_Timing_Init()
401 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
402 … ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
403 … ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
404 … Timing->AccessMode | in FMC_NORSRAM_Extended_Timing_Init()
405 … ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); in FMC_NORSRAM_Extended_Timing_Init()
407 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
408 … ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
409 … ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
410 Timing->AccessMode)); in FMC_NORSRAM_Extended_Timing_Init()
566 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_CommonSpace_Timing_Init() argument
570 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
571 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
572 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
573 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
580 Device->PMEM = (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
581 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
582 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
583 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); in FMC_NAND_CommonSpace_Timing_Init()
597 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_AttributeSpace_Timing_Init() argument
601 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
602 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
603 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
604 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
611 Device->PATT = (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
612 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
613 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
614 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); in FMC_NAND_AttributeSpace_Timing_Init()
866 const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_SDRAM_Timing_Init() argument
870 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); in FMC_SDRAM_Timing_Init()
871 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); in FMC_SDRAM_Timing_Init()
872 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); in FMC_SDRAM_Timing_Init()
873 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); in FMC_SDRAM_Timing_Init()
874 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); in FMC_SDRAM_Timing_Init()
875 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); in FMC_SDRAM_Timing_Init()
876 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); in FMC_SDRAM_Timing_Init()
884 (((Timing->LoadToActiveDelay) - 1U) | in FMC_SDRAM_Timing_Init()
885 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) | in FMC_SDRAM_Timing_Init()
886 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) | in FMC_SDRAM_Timing_Init()
887 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) | in FMC_SDRAM_Timing_Init()
888 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) | in FMC_SDRAM_Timing_Init()
889 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos) | in FMC_SDRAM_Timing_Init()
890 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos))); in FMC_SDRAM_Timing_Init()
897 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) | in FMC_SDRAM_Timing_Init()
898 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos)); in FMC_SDRAM_Timing_Init()
902 (((Timing->LoadToActiveDelay) - 1U) | in FMC_SDRAM_Timing_Init()
903 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) | in FMC_SDRAM_Timing_Init()
904 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) | in FMC_SDRAM_Timing_Init()
905 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) | in FMC_SDRAM_Timing_Init()
906 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos))); in FMC_SDRAM_Timing_Init()