Lines Matching refs:Init
196 const FMC_NORSRAM_InitTypeDef *Init) in FMC_NORSRAM_Init() argument
204 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
205 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
206 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
207 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
208 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
209 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
210 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
211 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
212 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
213 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); in FMC_NORSRAM_Init()
214 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); in FMC_NORSRAM_Init()
215 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); in FMC_NORSRAM_Init()
216 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); in FMC_NORSRAM_Init()
217 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); in FMC_NORSRAM_Init()
218 assert_param(IS_FMC_PAGESIZE(Init->PageSize)); in FMC_NORSRAM_Init()
221 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
224 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) in FMC_NORSRAM_Init()
234 Init->DataAddressMux | \ in FMC_NORSRAM_Init()
235 Init->MemoryType | \ in FMC_NORSRAM_Init()
236 Init->MemoryDataWidth | \ in FMC_NORSRAM_Init()
237 Init->BurstAccessMode | \ in FMC_NORSRAM_Init()
238 Init->WaitSignalPolarity | \ in FMC_NORSRAM_Init()
239 Init->WaitSignalActive | \ in FMC_NORSRAM_Init()
240 Init->WriteOperation | \ in FMC_NORSRAM_Init()
241 Init->WaitSignal | \ in FMC_NORSRAM_Init()
242 Init->ExtendedMode | \ in FMC_NORSRAM_Init()
243 Init->AsynchronousWait | \ in FMC_NORSRAM_Init()
244 Init->WriteBurst); in FMC_NORSRAM_Init()
246 btcr_reg |= Init->ContinuousClock; in FMC_NORSRAM_Init()
247 btcr_reg |= Init->WriteFifo; in FMC_NORSRAM_Init()
248 btcr_reg |= Init->PageSize; in FMC_NORSRAM_Init()
268 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
271 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN… in FMC_NORSRAM_Init()
273 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
276 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
279 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
533 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) in FMC_NAND_Init() argument
537 assert_param(IS_FMC_NAND_BANK(Init->NandBank)); in FMC_NAND_Init()
538 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); in FMC_NAND_Init()
539 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NAND_Init()
540 assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); in FMC_NAND_Init()
541 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); in FMC_NAND_Init()
542 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); in FMC_NAND_Init()
543 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); in FMC_NAND_Init()
546 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
548 Init->MemoryDataWidth | in FMC_NAND_Init()
549 Init->EccComputation | in FMC_NAND_Init()
550 Init->ECCPageSize | in FMC_NAND_Init()
551 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | in FMC_NAND_Init()
552 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); in FMC_NAND_Init()
803 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) in FMC_SDRAM_Init() argument
807 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); in FMC_SDRAM_Init()
808 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); in FMC_SDRAM_Init()
809 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); in FMC_SDRAM_Init()
810 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_SDRAM_Init()
811 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); in FMC_SDRAM_Init()
812 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); in FMC_SDRAM_Init()
813 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); in FMC_SDRAM_Init()
814 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); in FMC_SDRAM_Init()
815 assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); in FMC_SDRAM_Init()
816 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); in FMC_SDRAM_Init()
819 if (Init->SDBank == FMC_SDRAM_BANK1) in FMC_SDRAM_Init()
823 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
824 Init->RowBitsNumber | in FMC_SDRAM_Init()
825 Init->MemoryDataWidth | in FMC_SDRAM_Init()
826 Init->InternalBankNumber | in FMC_SDRAM_Init()
827 Init->CASLatency | in FMC_SDRAM_Init()
828 Init->WriteProtection | in FMC_SDRAM_Init()
829 Init->SDClockPeriod | in FMC_SDRAM_Init()
830 Init->ReadBurst | in FMC_SDRAM_Init()
831 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
839 (Init->SDClockPeriod | in FMC_SDRAM_Init()
840 Init->ReadBurst | in FMC_SDRAM_Init()
841 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
845 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
846 Init->RowBitsNumber | in FMC_SDRAM_Init()
847 Init->MemoryDataWidth | in FMC_SDRAM_Init()
848 Init->InternalBankNumber | in FMC_SDRAM_Init()
849 Init->CASLatency | in FMC_SDRAM_Init()
850 Init->WriteProtection)); in FMC_SDRAM_Init()