195 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Init()  argument
203   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Init()
221   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FMC_NORSRAM_Init()
268   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FMC_NORSRAM_Init()
273     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);  in FMC_NORSRAM_Init()
279     SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));  in FMC_NORSRAM_Init()
292 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_DeInit()  argument
296   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_DeInit()
301   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
307     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
312     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
315   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
329 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Timing_Init()  argument
335   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Timing_Init()
346   Device->BTCR[Bank + 1U] =  in FMC_NORSRAM_Timing_Init()
356   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))  in FMC_NORSRAM_Timing_Init()
358     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos));  in FMC_NORSRAM_Timing_Init()
360     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr);  in FMC_NORSRAM_Timing_Init()
378 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,  in FMC_NORSRAM_Extended_Timing_Init()  argument
389     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  in FMC_NORSRAM_Extended_Timing_Init()
401 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
407 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
415     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
445 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
448   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Enable()
452   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
463 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
466   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Disable()
470   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
533 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init)  in FMC_NAND_Init()  argument
536   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_Init()
546   MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |  in FMC_NAND_Init()
565 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_CommonSpace_Timing_Init()  argument
569   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_CommonSpace_Timing_Init()
580   Device->PMEM = (Timing->SetupTime |  in FMC_NAND_CommonSpace_Timing_Init()
596 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_AttributeSpace_Timing_Init()  argument
600   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_AttributeSpace_Timing_Init()
611   Device->PATT = (Timing->SetupTime |  in FMC_NAND_AttributeSpace_Timing_Init()
625 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
628   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_DeInit()
632   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
639   WRITE_REG(Device->PCR,  0x00000018U);  in FMC_NAND_DeInit()
640   WRITE_REG(Device->SR,   0x00000040U);  in FMC_NAND_DeInit()
641   WRITE_REG(Device->PMEM, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
642   WRITE_REG(Device->PATT, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
673 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
676   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Enable()
683   SET_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Enable()
695 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
698   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Disable()
705   CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Disable()
718 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
724   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_GetECC()
731   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
747   *ECCval = (uint32_t)Device->ECCR;  in FMC_NAND_GetECC()
803 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init)  in FMC_SDRAM_Init()  argument
806   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_Init()
821     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],  in FMC_SDRAM_Init()
835     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],  in FMC_SDRAM_Init()
843     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],  in FMC_SDRAM_Init()
865 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,  in FMC_SDRAM_Timing_Init()  argument
869   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_Timing_Init()
882     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],  in FMC_SDRAM_Timing_Init()
894     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],  in FMC_SDRAM_Timing_Init()
900     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],  in FMC_SDRAM_Timing_Init()
917 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_DeInit()  argument
920   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_DeInit()
924   Device->SDCR[Bank] = 0x000002D0U;  in FMC_SDRAM_DeInit()
925   Device->SDTR[Bank] = 0x0FFFFFFFU;  in FMC_SDRAM_DeInit()
926   Device->SDCMR      = 0x00000000U;  in FMC_SDRAM_DeInit()
927   Device->SDRTR      = 0x00000000U;  in FMC_SDRAM_DeInit()
928   Device->SDSR       = 0x00000000U;  in FMC_SDRAM_DeInit()
958 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Enable()  argument
961   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_WriteProtection_Enable()
965   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Enable()
975 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Disable()  argument
978   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_WriteProtection_Disable()
982   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Disable()
995 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,  in FMC_SDRAM_SendCommand()  argument
999   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_SendCommand()
1006 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC…  in FMC_SDRAM_SendCommand()
1021 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)  in FMC_SDRAM_ProgramRefreshRate()  argument
1024   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_ProgramRefreshRate()
1028   MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));  in FMC_SDRAM_ProgramRefreshRate()
1039 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,  in FMC_SDRAM_SetAutoRefreshNumber()  argument
1043   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_SetAutoRefreshNumber()
1047   MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));  in FMC_SDRAM_SetAutoRefreshNumber()
1061 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_GetModeStatus()  argument
1066   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_GetModeStatus()
1072     tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);  in FMC_SDRAM_GetModeStatus()
1076     tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);  in FMC_SDRAM_GetModeStatus()