Lines Matching refs:hxspi
302 static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, F…
304 static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pC…
338 HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_Init() argument
344 if (hxspi == NULL) in HAL_XSPI_Init()
352 assert_param(IS_XSPI_MEMORY_MODE(hxspi->Init.MemoryMode)); in HAL_XSPI_Init()
353 assert_param(IS_XSPI_MEMORY_TYPE(hxspi->Init.MemoryType)); in HAL_XSPI_Init()
354 assert_param(IS_XSPI_MEMORY_SIZE(hxspi->Init.MemorySize)); in HAL_XSPI_Init()
355 assert_param(IS_XSPI_CS_HIGH_TIME_CYCLE(hxspi->Init.ChipSelectHighTimeCycle)); in HAL_XSPI_Init()
356 assert_param(IS_XSPI_FREE_RUN_CLK(hxspi->Init.FreeRunningClock)); in HAL_XSPI_Init()
357 assert_param(IS_XSPI_CLOCK_MODE(hxspi->Init.ClockMode)); in HAL_XSPI_Init()
358 assert_param(IS_XSPI_WRAP_SIZE(hxspi->Init.WrapSize)); in HAL_XSPI_Init()
359 assert_param(IS_XSPI_CLK_PRESCALER(hxspi->Init.ClockPrescaler)); in HAL_XSPI_Init()
360 assert_param(IS_XSPI_SAMPLE_SHIFTING(hxspi->Init.SampleShifting)); in HAL_XSPI_Init()
361 assert_param(IS_XSPI_DHQC(hxspi->Init.DelayHoldQuarterCycle)); in HAL_XSPI_Init()
362 assert_param(IS_XSPI_CS_BOUND(hxspi->Init.ChipSelectBoundary)); in HAL_XSPI_Init()
363 assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); in HAL_XSPI_Init()
364 assert_param(IS_XSPI_MAXTRAN(hxspi->Init.MaxTran)); in HAL_XSPI_Init()
365 assert_param(IS_XSPI_CSSEL(hxspi->Init.MemorySelect)); in HAL_XSPI_Init()
367 hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; in HAL_XSPI_Init()
370 if (hxspi->State == HAL_XSPI_STATE_RESET) in HAL_XSPI_Init()
374 hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; in HAL_XSPI_Init()
375 hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; in HAL_XSPI_Init()
376 hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; in HAL_XSPI_Init()
377 hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; in HAL_XSPI_Init()
378 hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; in HAL_XSPI_Init()
379 hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; in HAL_XSPI_Init()
380 hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; in HAL_XSPI_Init()
381 hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; in HAL_XSPI_Init()
382 hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; in HAL_XSPI_Init()
383 hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; in HAL_XSPI_Init()
385 if (hxspi->MspInitCallback == NULL) in HAL_XSPI_Init()
387 hxspi->MspInitCallback = HAL_XSPI_MspInit; in HAL_XSPI_Init()
391 hxspi->MspInitCallback(hxspi); in HAL_XSPI_Init()
394 HAL_XSPI_MspInit(hxspi); in HAL_XSPI_Init()
398 (void)HAL_XSPI_SetTimeout(hxspi, HAL_XSPI_TIMEOUT_DEFAULT_VALUE); in HAL_XSPI_Init()
401 MODIFY_REG(hxspi->Instance->DCR1, in HAL_XSPI_Init()
403 (hxspi->Init.MemoryType | ((hxspi->Init.MemorySize) << XSPI_DCR1_DEVSIZE_Pos) | in HAL_XSPI_Init()
404 … ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); in HAL_XSPI_Init()
407 MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_WRAPSIZE, hxspi->Init.WrapSize); in HAL_XSPI_Init()
410 …MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_CSBOUND, (hxspi->Init.ChipSelectBoundary << XSPI_DCR3_… in HAL_XSPI_Init()
413 MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_MAXTRAN, \ in HAL_XSPI_Init()
414 (hxspi->Init.MaxTran << XSPI_DCR3_MAXTRAN_Pos)); in HAL_XSPI_Init()
417 hxspi->Instance->DCR4 = hxspi->Init.Refresh; in HAL_XSPI_Init()
420 …MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_F… in HAL_XSPI_Init()
423 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Init()
428 MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, in HAL_XSPI_Init()
429 ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); in HAL_XSPI_Init()
431 if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
435 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Init()
442 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_DMM | XSPI_CR_CSSEL), in HAL_XSPI_Init()
443 (hxspi->Init.MemoryMode | hxspi->Init.MemorySelect)); in HAL_XSPI_Init()
446 MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT | XSPI_TCR_DHQC), in HAL_XSPI_Init()
447 (hxspi->Init.SampleShifting | hxspi->Init.DelayHoldQuarterCycle)); in HAL_XSPI_Init()
450 HAL_XSPI_ENABLE(hxspi); in HAL_XSPI_Init()
453 if (hxspi->Init.FreeRunningClock == HAL_XSPI_FREERUNCLK_ENABLE) in HAL_XSPI_Init()
455 SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_Init()
459 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Init()
461 hxspi->State = HAL_XSPI_STATE_HYPERBUS_INIT; in HAL_XSPI_Init()
465 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Init()
478 __weak void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_MspInit() argument
481 UNUSED(hxspi); in HAL_XSPI_MspInit()
493 HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_DeInit() argument
498 if (hxspi == NULL) in HAL_XSPI_DeInit()
506 HAL_XSPI_DISABLE(hxspi); in HAL_XSPI_DeInit()
509 CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DeInit()
512 if (hxspi->MspDeInitCallback == NULL) in HAL_XSPI_DeInit()
514 hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; in HAL_XSPI_DeInit()
518 hxspi->MspDeInitCallback(hxspi); in HAL_XSPI_DeInit()
521 HAL_XSPI_MspDeInit(hxspi); in HAL_XSPI_DeInit()
525 hxspi->State = HAL_XSPI_STATE_RESET; in HAL_XSPI_DeInit()
536 __weak void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_MspDeInit() argument
539 UNUSED(hxspi); in HAL_XSPI_MspDeInit()
576 void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_IRQHandler() argument
578 __IO uint32_t *data_reg = &hxspi->Instance->DR; in HAL_XSPI_IRQHandler()
579 uint32_t flag = hxspi->Instance->SR; in HAL_XSPI_IRQHandler()
580 uint32_t itsource = hxspi->Instance->CR; in HAL_XSPI_IRQHandler()
581 uint32_t currentstate = hxspi->State; in HAL_XSPI_IRQHandler()
589 *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; in HAL_XSPI_IRQHandler()
590 hxspi->pBuffPtr++; in HAL_XSPI_IRQHandler()
591 hxspi->XferCount--; in HAL_XSPI_IRQHandler()
596 *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); in HAL_XSPI_IRQHandler()
597 hxspi->pBuffPtr++; in HAL_XSPI_IRQHandler()
598 hxspi->XferCount--; in HAL_XSPI_IRQHandler()
605 if (hxspi->XferCount == 0U) in HAL_XSPI_IRQHandler()
609 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_FT); in HAL_XSPI_IRQHandler()
614 hxspi->FifoThresholdCallback(hxspi); in HAL_XSPI_IRQHandler()
616 HAL_XSPI_FifoThresholdCallback(hxspi); in HAL_XSPI_IRQHandler()
624 if ((hxspi->XferCount > 0U) && ((flag & XSPI_SR_FLEVEL) != 0U)) in HAL_XSPI_IRQHandler()
627 *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); in HAL_XSPI_IRQHandler()
628 hxspi->pBuffPtr++; in HAL_XSPI_IRQHandler()
629 hxspi->XferCount--; in HAL_XSPI_IRQHandler()
631 else if (hxspi->XferCount == 0U) in HAL_XSPI_IRQHandler()
634 hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; in HAL_XSPI_IRQHandler()
637 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_IRQHandler()
639 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
643 hxspi->RxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
645 HAL_XSPI_RxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
656 hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; in HAL_XSPI_IRQHandler()
659 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_IRQHandler()
661 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
667 hxspi->TxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
669 HAL_XSPI_TxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
676 hxspi->CmdCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
678 HAL_XSPI_CmdCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
683 if (hxspi->ErrorCode == HAL_XSPI_ERROR_NONE) in HAL_XSPI_IRQHandler()
688 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
690 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
698 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
700 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
714 hxspi->Instance->FCR = HAL_XSPI_FLAG_SM; in HAL_XSPI_IRQHandler()
717 if ((hxspi->Instance->CR & XSPI_CR_APMS) != 0U) in HAL_XSPI_IRQHandler()
720 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); in HAL_XSPI_IRQHandler()
722 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
727 hxspi->StatusMatchCallback(hxspi); in HAL_XSPI_IRQHandler()
729 HAL_XSPI_StatusMatchCallback(hxspi); in HAL_XSPI_IRQHandler()
736 hxspi->Instance->FCR = HAL_XSPI_FLAG_TE; in HAL_XSPI_IRQHandler()
739 …HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HA… in HAL_XSPI_IRQHandler()
742 hxspi->ErrorCode = HAL_XSPI_ERROR_TRANSFER; in HAL_XSPI_IRQHandler()
745 if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) in HAL_XSPI_IRQHandler()
748 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_IRQHandler()
751 hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_IRQHandler()
752 if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) in HAL_XSPI_IRQHandler()
754 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
758 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
760 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
765 hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_IRQHandler()
766 if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) in HAL_XSPI_IRQHandler()
768 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
772 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
774 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
780 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
784 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
786 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
794 hxspi->Instance->FCR = HAL_XSPI_FLAG_TO; in HAL_XSPI_IRQHandler()
798 hxspi->TimeOutCallback(hxspi); in HAL_XSPI_IRQHandler()
800 HAL_XSPI_TimeOutCallback(hxspi); in HAL_XSPI_IRQHandler()
816 HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, u… in HAL_XSPI_Command() argument
824 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in HAL_XSPI_Command()
850 assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); in HAL_XSPI_Command()
865 state = hxspi->State; in HAL_XSPI_Command()
866 …if (((state == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERB… in HAL_XSPI_Command()
874 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_Command()
879 hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; in HAL_XSPI_Command()
882 status = XSPI_ConfigCmd(hxspi, pCmd); in HAL_XSPI_Command()
890 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_XSPI_Command()
892 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Command()
899 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_Command()
903 if (hxspi->State == HAL_XSPI_STATE_WRITE_CMD_CFG) in HAL_XSPI_Command()
905 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_Command()
909 hxspi->State = HAL_XSPI_STATE_READ_CMD_CFG; in HAL_XSPI_Command()
914 if (hxspi->State == HAL_XSPI_STATE_READ_CMD_CFG) in HAL_XSPI_Command()
916 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_Command()
920 hxspi->State = HAL_XSPI_STATE_WRITE_CMD_CFG; in HAL_XSPI_Command()
938 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Command()
951 HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd) in HAL_XSPI_Command_IT() argument
959 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in HAL_XSPI_Command_IT()
985 assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); in HAL_XSPI_Command_IT()
997 …if ((hxspi->State == HAL_XSPI_STATE_READY) && (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_… in HAL_XSPI_Command_IT()
998 … (pCmd->DataMode == HAL_XSPI_DATA_NONE) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) in HAL_XSPI_Command_IT()
1001 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Command_IT()
1006 hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; in HAL_XSPI_Command_IT()
1009 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Command_IT()
1012 status = XSPI_ConfigCmd(hxspi, pCmd); in HAL_XSPI_Command_IT()
1017 hxspi->State = HAL_XSPI_STATE_BUSY_CMD; in HAL_XSPI_Command_IT()
1020 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_TE); in HAL_XSPI_Command_IT()
1027 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Command_IT()
1040 HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pC… in HAL_XSPI_HyperbusCfg() argument
1054 state = hxspi->State; in HAL_XSPI_HyperbusCfg()
1058 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_HyperbusCfg()
1063 WRITE_REG(hxspi->Instance->HLCR, ((pCfg->RWRecoveryTimeCycle << XSPI_HLCR_TRWR_Pos) | in HAL_XSPI_HyperbusCfg()
1068 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_HyperbusCfg()
1078 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_HyperbusCfg()
1091 HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pC… in HAL_XSPI_HyperbusCmd() argument
1102 assert_param(IS_XSPI_DATA_MODE(hxspi->Init.MemoryType, pCmd->DataMode)); in HAL_XSPI_HyperbusCmd()
1105 …if ((hxspi->State == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS… in HAL_XSPI_HyperbusCmd()
1108 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_HyperbusCmd()
1113 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); in HAL_XSPI_HyperbusCmd()
1116 MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP_0, pCmd->AddressSpace); in HAL_XSPI_HyperbusCmd()
1122 WRITE_REG(hxspi->Instance->CCR, (pCmd->DQSMode | XSPI_CCR_DDTR | pCmd->DataMode | in HAL_XSPI_HyperbusCmd()
1124 WRITE_REG(hxspi->Instance->WCCR, (pCmd->DQSMode | XSPI_WCCR_DDTR | pCmd->DataMode | in HAL_XSPI_HyperbusCmd()
1128 WRITE_REG(hxspi->Instance->DLR, (pCmd->DataLength - 1U)); in HAL_XSPI_HyperbusCmd()
1131 WRITE_REG(hxspi->Instance->AR, pCmd->Address); in HAL_XSPI_HyperbusCmd()
1134 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_HyperbusCmd()
1144 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_HyperbusCmd()
1158 HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeo… in HAL_XSPI_Transmit() argument
1162 __IO uint32_t *data_reg = &hxspi->Instance->DR; in HAL_XSPI_Transmit()
1168 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit()
1173 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Transmit()
1176 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Transmit()
1177 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Transmit()
1178 hxspi->pBuffPtr = (uint8_t *)pData; in HAL_XSPI_Transmit()
1181 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_XSPI_Transmit()
1186 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_FT, SET, tickstart, Timeout); in HAL_XSPI_Transmit()
1193 *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; in HAL_XSPI_Transmit()
1194 hxspi->pBuffPtr++; in HAL_XSPI_Transmit()
1195 hxspi->XferCount--; in HAL_XSPI_Transmit()
1196 } while (hxspi->XferCount > 0U); in HAL_XSPI_Transmit()
1201 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_XSPI_Transmit()
1206 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Transmit()
1208 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Transmit()
1215 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Transmit()
1230 HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeou… in HAL_XSPI_Receive() argument
1234 __IO uint32_t *data_reg = &hxspi->Instance->DR; in HAL_XSPI_Receive()
1235 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_Receive()
1236 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_Receive()
1242 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive()
1247 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Receive()
1250 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Receive()
1251 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Receive()
1252 hxspi->pBuffPtr = pData; in HAL_XSPI_Receive()
1255 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_XSPI_Receive()
1258 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Receive()
1260 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive()
1264 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_Receive()
1266 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive()
1270 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_Receive()
1277 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, (HAL_XSPI_FLAG_FT | HAL_XSPI_FLAG_TC), SET, ticksta… in HAL_XSPI_Receive()
1284 *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); in HAL_XSPI_Receive()
1285 hxspi->pBuffPtr++; in HAL_XSPI_Receive()
1286 hxspi->XferCount--; in HAL_XSPI_Receive()
1287 } while (hxspi->XferCount > 0U); in HAL_XSPI_Receive()
1292 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_XSPI_Receive()
1297 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Receive()
1299 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Receive()
1306 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Receive()
1320 HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) in HAL_XSPI_Transmit_IT() argument
1328 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_IT()
1333 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Transmit_IT()
1336 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Transmit_IT()
1337 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Transmit_IT()
1338 hxspi->pBuffPtr = (uint8_t *)pData; in HAL_XSPI_Transmit_IT()
1341 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_XSPI_Transmit_IT()
1344 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Transmit_IT()
1347 hxspi->State = HAL_XSPI_STATE_BUSY_TX; in HAL_XSPI_Transmit_IT()
1350 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_Transmit_IT()
1355 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Transmit_IT()
1369 HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) in HAL_XSPI_Receive_IT() argument
1372 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_Receive_IT()
1373 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_Receive_IT()
1379 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_IT()
1384 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Receive_IT()
1387 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Receive_IT()
1388 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Receive_IT()
1389 hxspi->pBuffPtr = pData; in HAL_XSPI_Receive_IT()
1392 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_XSPI_Receive_IT()
1395 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Receive_IT()
1398 hxspi->State = HAL_XSPI_STATE_BUSY_RX; in HAL_XSPI_Receive_IT()
1401 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_Receive_IT()
1404 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Receive_IT()
1406 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_IT()
1410 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_Receive_IT()
1412 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_IT()
1416 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_Receive_IT()
1423 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Receive_IT()
1441 HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) in HAL_XSPI_Transmit_DMA() argument
1444 uint32_t data_size = hxspi->Instance->DLR + 1U; in HAL_XSPI_Transmit_DMA()
1452 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1457 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Transmit_DMA()
1459 if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Transmit_DMA()
1461 p_queue = hxspi->hdmatx->LinkedListQueue; in HAL_XSPI_Transmit_DMA()
1469 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Transmit_DMA()
1477 data_width = hxspi->hdmatx->Init.DestDataWidth; in HAL_XSPI_Transmit_DMA()
1482 hxspi->XferCount = data_size; in HAL_XSPI_Transmit_DMA()
1486 if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) in HAL_XSPI_Transmit_DMA()
1490 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1495 hxspi->XferCount = data_size; in HAL_XSPI_Transmit_DMA()
1500 if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) in HAL_XSPI_Transmit_DMA()
1504 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1509 hxspi->XferCount = data_size; in HAL_XSPI_Transmit_DMA()
1519 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Transmit_DMA()
1520 hxspi->pBuffPtr = (uint8_t *)pData; in HAL_XSPI_Transmit_DMA()
1523 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_XSPI_Transmit_DMA()
1526 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Transmit_DMA()
1529 hxspi->State = HAL_XSPI_STATE_BUSY_TX; in HAL_XSPI_Transmit_DMA()
1532 hxspi->hdmatx->XferCpltCallback = XSPI_DMACplt; in HAL_XSPI_Transmit_DMA()
1535 hxspi->hdmatx->XferHalfCpltCallback = XSPI_DMAHalfCplt; in HAL_XSPI_Transmit_DMA()
1538 hxspi->hdmatx->XferErrorCallback = XSPI_DMAError; in HAL_XSPI_Transmit_DMA()
1541 hxspi->hdmatx->XferAbortCallback = NULL; in HAL_XSPI_Transmit_DMA()
1544 if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Transmit_DMA()
1546 if (hxspi->hdmatx->LinkedListQueue != NULL) in HAL_XSPI_Transmit_DMA()
1554 p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; in HAL_XSPI_Transmit_DMA()
1558 p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; in HAL_XSPI_Transmit_DMA()
1560 status = HAL_DMAEx_List_Start_IT(hxspi->hdmatx); in HAL_XSPI_Transmit_DMA()
1565 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Transmit_DMA()
1567 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Transmit_DMA()
1575 if ((hxspi->hdmatx->Init.Direction == DMA_MEMORY_TO_PERIPH) && in HAL_XSPI_Transmit_DMA()
1576 …(hxspi->hdmatx->Init.SrcInc == DMA_SINC_INCREMENTED) && (hxspi->hdmatx->Init.DestInc == DMA_DINC_F… in HAL_XSPI_Transmit_DMA()
1578 …status = HAL_DMA_Start_IT(hxspi->hdmatx, (uint32_t)pData, (uint32_t)&hxspi->Instance->DR, hxspi->X… in HAL_XSPI_Transmit_DMA()
1583 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1590 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); in HAL_XSPI_Transmit_DMA()
1593 SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Transmit_DMA()
1598 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Transmit_DMA()
1599 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Transmit_DMA()
1606 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Transmit_DMA()
1624 HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) in HAL_XSPI_Receive_DMA() argument
1627 uint32_t data_size = hxspi->Instance->DLR + 1U; in HAL_XSPI_Receive_DMA()
1628 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_Receive_DMA()
1629 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_Receive_DMA()
1637 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1642 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Receive_DMA()
1644 if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Receive_DMA()
1646 p_queue = hxspi->hdmarx->LinkedListQueue; in HAL_XSPI_Receive_DMA()
1654 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Receive_DMA()
1662 data_width = hxspi->hdmarx->Init.DestDataWidth; in HAL_XSPI_Receive_DMA()
1668 hxspi->XferCount = data_size; in HAL_XSPI_Receive_DMA()
1672 if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) in HAL_XSPI_Receive_DMA()
1676 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1681 hxspi->XferCount = data_size; in HAL_XSPI_Receive_DMA()
1686 if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) in HAL_XSPI_Receive_DMA()
1690 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1695 hxspi->XferCount = data_size; in HAL_XSPI_Receive_DMA()
1705 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Receive_DMA()
1706 hxspi->pBuffPtr = pData; in HAL_XSPI_Receive_DMA()
1709 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_XSPI_Receive_DMA()
1712 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Receive_DMA()
1715 hxspi->State = HAL_XSPI_STATE_BUSY_RX; in HAL_XSPI_Receive_DMA()
1718 hxspi->hdmarx->XferCpltCallback = XSPI_DMACplt; in HAL_XSPI_Receive_DMA()
1721 hxspi->hdmarx->XferHalfCpltCallback = XSPI_DMAHalfCplt; in HAL_XSPI_Receive_DMA()
1724 hxspi->hdmarx->XferErrorCallback = XSPI_DMAError; in HAL_XSPI_Receive_DMA()
1727 hxspi->hdmarx->XferAbortCallback = NULL; in HAL_XSPI_Receive_DMA()
1730 if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Receive_DMA()
1732 if (hxspi->hdmarx->LinkedListQueue != NULL) in HAL_XSPI_Receive_DMA()
1740 p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; in HAL_XSPI_Receive_DMA()
1742 p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; in HAL_XSPI_Receive_DMA()
1746 status = HAL_DMAEx_List_Start_IT(hxspi->hdmarx); in HAL_XSPI_Receive_DMA()
1751 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Receive_DMA()
1753 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Receive_DMA()
1761 …if ((hxspi->hdmarx->Init.Direction == DMA_PERIPH_TO_MEMORY) && (hxspi->hdmarx->Init.SrcInc == DMA_… in HAL_XSPI_Receive_DMA()
1762 && (hxspi->hdmarx->Init.DestInc == DMA_DINC_INCREMENTED)) in HAL_XSPI_Receive_DMA()
1764 …status = HAL_DMA_Start_IT(hxspi->hdmarx, (uint32_t)&hxspi->Instance->DR, (uint32_t)pData, hxspi->X… in HAL_XSPI_Receive_DMA()
1769 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1776 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); in HAL_XSPI_Receive_DMA()
1779 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Receive_DMA()
1781 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_DMA()
1785 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_Receive_DMA()
1787 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_DMA()
1791 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_Receive_DMA()
1796 SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Receive_DMA()
1801 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Receive_DMA()
1802 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Receive_DMA()
1809 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Receive_DMA()
1824 HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pC… in HAL_XSPI_AutoPolling() argument
1829 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_AutoPolling()
1830 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_AutoPolling()
1832 uint32_t dlr_reg = hxspi->Instance->DLR; in HAL_XSPI_AutoPolling()
1842 …if ((hxspi->State == HAL_XSPI_STATE_CMD_CFG) && (pCfg->AutomaticStop == HAL_XSPI_AUTOMATIC_STOP_EN… in HAL_XSPI_AutoPolling()
1845 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_AutoPolling()
1850 WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); in HAL_XSPI_AutoPolling()
1851 WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); in HAL_XSPI_AutoPolling()
1852 WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); in HAL_XSPI_AutoPolling()
1853 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), in HAL_XSPI_AutoPolling()
1857 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_AutoPolling()
1859 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling()
1863 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_AutoPolling()
1865 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling()
1869 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_AutoPolling()
1874 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_SM, SET, tickstart, Timeout); in HAL_XSPI_AutoPolling()
1879 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_SM); in HAL_XSPI_AutoPolling()
1881 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_AutoPolling()
1892 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_AutoPolling()
1905 HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const… in HAL_XSPI_AutoPolling_IT() argument
1909 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_AutoPolling_IT()
1910 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_AutoPolling_IT()
1912 uint32_t dlr_reg = hxspi->Instance->DLR; in HAL_XSPI_AutoPolling_IT()
1922 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_AutoPolling_IT()
1925 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_AutoPolling_IT()
1930 WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); in HAL_XSPI_AutoPolling_IT()
1931 WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); in HAL_XSPI_AutoPolling_IT()
1932 WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); in HAL_XSPI_AutoPolling_IT()
1933 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), in HAL_XSPI_AutoPolling_IT()
1937 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_SM); in HAL_XSPI_AutoPolling_IT()
1939 hxspi->State = HAL_XSPI_STATE_BUSY_AUTO_POLLING; in HAL_XSPI_AutoPolling_IT()
1942 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); in HAL_XSPI_AutoPolling_IT()
1945 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_AutoPolling_IT()
1947 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling_IT()
1951 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_AutoPolling_IT()
1953 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling_IT()
1957 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_AutoPolling_IT()
1965 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_AutoPolling_IT()
1978 HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const … in HAL_XSPI_MemoryMapped() argument
1987 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_MemoryMapped()
1990 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_MemoryMapped()
1994 hxspi->State = HAL_XSPI_STATE_BUSY_MEM_MAPPED; in HAL_XSPI_MemoryMapped()
2001 WRITE_REG(hxspi->Instance->LPTR, pCfg->TimeoutPeriodClock); in HAL_XSPI_MemoryMapped()
2004 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TO); in HAL_XSPI_MemoryMapped()
2007 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TO); in HAL_XSPI_MemoryMapped()
2011 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_TCEN | XSPI_CR_FMODE), in HAL_XSPI_MemoryMapped()
2018 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_MemoryMapped()
2029 __weak void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_ErrorCallback() argument
2032 UNUSED(hxspi); in HAL_XSPI_ErrorCallback()
2044 __weak void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_AbortCpltCallback() argument
2047 UNUSED(hxspi); in HAL_XSPI_AbortCpltCallback()
2059 __weak void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_FifoThresholdCallback() argument
2062 UNUSED(hxspi); in HAL_XSPI_FifoThresholdCallback()
2074 __weak void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_CmdCpltCallback() argument
2077 UNUSED(hxspi); in HAL_XSPI_CmdCpltCallback()
2089 __weak void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_RxCpltCallback() argument
2092 UNUSED(hxspi); in HAL_XSPI_RxCpltCallback()
2104 __weak void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_TxCpltCallback() argument
2107 UNUSED(hxspi); in HAL_XSPI_TxCpltCallback()
2119 __weak void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_RxHalfCpltCallback() argument
2122 UNUSED(hxspi); in HAL_XSPI_RxHalfCpltCallback()
2134 __weak void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_TxHalfCpltCallback() argument
2137 UNUSED(hxspi); in HAL_XSPI_TxHalfCpltCallback()
2149 __weak void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_StatusMatchCallback() argument
2152 UNUSED(hxspi); in HAL_XSPI_StatusMatchCallback()
2164 __weak void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_TimeOutCallback() argument
2167 UNUSED(hxspi); in HAL_XSPI_TimeOutCallback()
2196 HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef C… in HAL_XSPI_RegisterCallback() argument
2204 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2208 if (hxspi->State == HAL_XSPI_STATE_READY) in HAL_XSPI_RegisterCallback()
2213 hxspi->ErrorCallback = pCallback; in HAL_XSPI_RegisterCallback()
2216 hxspi->AbortCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2219 hxspi->FifoThresholdCallback = pCallback; in HAL_XSPI_RegisterCallback()
2222 hxspi->CmdCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2225 hxspi->RxCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2228 hxspi->TxCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2231 hxspi->RxHalfCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2234 hxspi->TxHalfCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2237 hxspi->StatusMatchCallback = pCallback; in HAL_XSPI_RegisterCallback()
2240 hxspi->TimeOutCallback = pCallback; in HAL_XSPI_RegisterCallback()
2243 hxspi->MspInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2246 hxspi->MspDeInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2250 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2256 else if (hxspi->State == HAL_XSPI_STATE_RESET) in HAL_XSPI_RegisterCallback()
2261 hxspi->MspInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2264 hxspi->MspDeInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2268 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2277 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2305 HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef… in HAL_XSPI_UnRegisterCallback() argument
2309 if (hxspi->State == HAL_XSPI_STATE_READY) in HAL_XSPI_UnRegisterCallback()
2314 hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; in HAL_XSPI_UnRegisterCallback()
2317 hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; in HAL_XSPI_UnRegisterCallback()
2320 hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; in HAL_XSPI_UnRegisterCallback()
2323 hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; in HAL_XSPI_UnRegisterCallback()
2326 hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; in HAL_XSPI_UnRegisterCallback()
2329 hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; in HAL_XSPI_UnRegisterCallback()
2332 hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; in HAL_XSPI_UnRegisterCallback()
2335 hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; in HAL_XSPI_UnRegisterCallback()
2338 hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; in HAL_XSPI_UnRegisterCallback()
2341 hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; in HAL_XSPI_UnRegisterCallback()
2344 hxspi->MspInitCallback = HAL_XSPI_MspInit; in HAL_XSPI_UnRegisterCallback()
2347 hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; in HAL_XSPI_UnRegisterCallback()
2351 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_UnRegisterCallback()
2357 else if (hxspi->State == HAL_XSPI_STATE_RESET) in HAL_XSPI_UnRegisterCallback()
2362 hxspi->MspInitCallback = HAL_XSPI_MspInit; in HAL_XSPI_UnRegisterCallback()
2365 hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; in HAL_XSPI_UnRegisterCallback()
2369 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_UnRegisterCallback()
2378 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_UnRegisterCallback()
2415 HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_Abort() argument
2421 if (hxspi->State != HAL_XSPI_STATE_RESET) in HAL_XSPI_Abort()
2424 if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) in HAL_XSPI_Abort()
2427 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Abort()
2430 status = HAL_DMA_Abort(hxspi->hdmatx); in HAL_XSPI_Abort()
2433 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Abort()
2437 status = HAL_DMA_Abort(hxspi->hdmarx); in HAL_XSPI_Abort()
2440 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Abort()
2444 if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) in HAL_XSPI_Abort()
2447 SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); in HAL_XSPI_Abort()
2450 … status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, hxspi->Timeout); in HAL_XSPI_Abort()
2455 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Abort()
2458 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Abort()
2463 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort()
2465 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort()
2472 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort()
2474 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort()
2480 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Abort()
2491 HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_Abort_IT() argument
2496 if (hxspi->State != HAL_XSPI_STATE_RESET) in HAL_XSPI_Abort_IT()
2499 …HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HA… in HAL_XSPI_Abort_IT()
2501 hxspi->State = HAL_XSPI_STATE_ABORT; in HAL_XSPI_Abort_IT()
2504 if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) in HAL_XSPI_Abort_IT()
2507 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Abort_IT()
2510 hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_Abort_IT()
2511 if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) in HAL_XSPI_Abort_IT()
2513 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort_IT()
2517 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2519 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2524 hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_Abort_IT()
2525 if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) in HAL_XSPI_Abort_IT()
2527 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort_IT()
2531 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2533 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2539 if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) in HAL_XSPI_Abort_IT()
2542 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Abort_IT()
2545 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); in HAL_XSPI_Abort_IT()
2548 SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); in HAL_XSPI_Abort_IT()
2551 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort_IT()
2556 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort_IT()
2558 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort_IT()
2562 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2564 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2572 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Abort_IT()
2583 HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold) in HAL_XSPI_SetFifoThreshold() argument
2590 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetFifoThreshold()
2593 hxspi->Init.FifoThresholdByte = Threshold; in HAL_XSPI_SetFifoThreshold()
2596 …MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_F… in HAL_XSPI_SetFifoThreshold()
2602 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetFifoThreshold()
2612 uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi) in HAL_XSPI_GetFifoThreshold() argument
2614 return ((READ_BIT(hxspi->Instance->CR, XSPI_CR_FTHRES) >> XSPI_CR_FTHRES_Pos) + 1U); in HAL_XSPI_GetFifoThreshold()
2622 HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type) in HAL_XSPI_SetMemoryType() argument
2629 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetMemoryType()
2632 hxspi->Init.MemoryType = Type; in HAL_XSPI_SetMemoryType()
2635 MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP, hxspi->Init.MemoryType); in HAL_XSPI_SetMemoryType()
2640 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetMemoryType()
2651 HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size) in HAL_XSPI_SetDeviceSize() argument
2658 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetDeviceSize()
2661 hxspi->Init.MemorySize = Size; in HAL_XSPI_SetDeviceSize()
2664 MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_DEVSIZE, in HAL_XSPI_SetDeviceSize()
2665 (hxspi->Init.MemorySize << XSPI_DCR1_DEVSIZE_Pos)); in HAL_XSPI_SetDeviceSize()
2670 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetDeviceSize()
2681 HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler) in HAL_XSPI_SetClockPrescaler() argument
2687 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetClockPrescaler()
2690 hxspi->Init.ClockPrescaler = Prescaler; in HAL_XSPI_SetClockPrescaler()
2693 MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, in HAL_XSPI_SetClockPrescaler()
2694 ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); in HAL_XSPI_SetClockPrescaler()
2699 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetClockPrescaler()
2710 HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout) in HAL_XSPI_SetTimeout() argument
2712 hxspi->Timeout = Timeout; in HAL_XSPI_SetTimeout()
2721 uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi) in HAL_XSPI_GetError() argument
2723 return hxspi->ErrorCode; in HAL_XSPI_GetError()
2731 uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi) in HAL_XSPI_GetState() argument
2734 return hxspi->State; in HAL_XSPI_GetState()
2763 HAL_StatusTypeDef HAL_XSPIM_Config(XSPI_HandleTypeDef *const hxspi, XSPIM_CfgTypeDef *const pCfg, u… in HAL_XSPIM_Config() argument
2803 if (hxspi->Instance == XSPI1) in HAL_XSPIM_Config()
2815 else if (hxspi->Instance == XSPI2) in HAL_XSPIM_Config()
2829 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPIM_Config()
2898 HAL_StatusTypeDef HAL_XSPI_GetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) in HAL_XSPI_GetDelayValue() argument
2903 if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_GetDelayValue()
2911 reg = hxspi->Instance->CALFCR; in HAL_XSPI_GetDelayValue()
2915 reg = hxspi->Instance->CALMR; in HAL_XSPI_GetDelayValue()
2918 reg = hxspi->Instance->CALSOR; in HAL_XSPI_GetDelayValue()
2921 reg = hxspi->Instance->CALSIR; in HAL_XSPI_GetDelayValue()
2925 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_GetDelayValue()
2938 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_GetDelayValue()
2950 HAL_StatusTypeDef HAL_XSPI_SetDelayValue(XSPI_HandleTypeDef *hxspi, XSPI_HSCalTypeDef *const pCfg) in HAL_XSPI_SetDelayValue() argument
2954 if (IS_XSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_SetDelayValue()
2962 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetDelayValue()
2967 MODIFY_REG(hxspi->Instance->CALMR, (XSPI_CALMR_COARSE | XSPI_CALMR_FINE), in HAL_XSPI_SetDelayValue()
2971 MODIFY_REG(hxspi->Instance->CALSOR, (XSPI_CALSOR_COARSE | XSPI_CALSOR_FINE), in HAL_XSPI_SetDelayValue()
2975 MODIFY_REG(hxspi->Instance->CALSIR, (XSPI_CALSIR_COARSE | XSPI_CALSIR_FINE), in HAL_XSPI_SetDelayValue()
2980 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_SetDelayValue()
2987 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetDelayValue()
2993 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_SetDelayValue()
3013 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMACplt() local
3014 hxspi->XferCount = 0; in XSPI_DMACplt()
3017 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in XSPI_DMACplt()
3020 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); in XSPI_DMACplt()
3030 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMAHalfCplt() local
3031 hxspi->XferCount = (hxspi->XferCount >> 1); in XSPI_DMAHalfCplt()
3033 if (hxspi->State == HAL_XSPI_STATE_BUSY_RX) in XSPI_DMAHalfCplt()
3036 hxspi->RxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
3038 HAL_XSPI_RxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
3044 hxspi->TxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
3046 HAL_XSPI_TxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
3058 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMAError() local
3059 hxspi->XferCount = 0; in XSPI_DMAError()
3060 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in XSPI_DMAError()
3063 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in XSPI_DMAError()
3066 if (HAL_XSPI_Abort_IT(hxspi) != HAL_OK) in XSPI_DMAError()
3069 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in XSPI_DMAError()
3071 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_DMAError()
3075 hxspi->ErrorCallback(hxspi); in XSPI_DMAError()
3077 HAL_XSPI_ErrorCallback(hxspi); in XSPI_DMAError()
3089 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMAAbortCplt() local
3090 hxspi->XferCount = 0; in XSPI_DMAAbortCplt()
3093 if (hxspi->State == HAL_XSPI_STATE_ABORT) in XSPI_DMAAbortCplt()
3096 if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) in XSPI_DMAAbortCplt()
3099 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in XSPI_DMAAbortCplt()
3102 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); in XSPI_DMAAbortCplt()
3105 SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); in XSPI_DMAAbortCplt()
3109 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_DMAAbortCplt()
3113 hxspi->AbortCpltCallback(hxspi); in XSPI_DMAAbortCplt()
3115 HAL_XSPI_AbortCpltCallback(hxspi); in XSPI_DMAAbortCplt()
3122 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_DMAAbortCplt()
3126 hxspi->ErrorCallback(hxspi); in XSPI_DMAAbortCplt()
3128 HAL_XSPI_ErrorCallback(hxspi); in XSPI_DMAAbortCplt()
3142 static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, in XSPI_WaitFlagStateUntilTimeout() argument
3146 while ((HAL_XSPI_GET_FLAG(hxspi, Flag)) != State) in XSPI_WaitFlagStateUntilTimeout()
3153 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_WaitFlagStateUntilTimeout()
3154 hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; in XSPI_WaitFlagStateUntilTimeout()
3169 static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *pCmd) in XSPI_ConfigCmd() argument
3178 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); in XSPI_ConfigCmd()
3180 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in XSPI_ConfigCmd()
3183 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_MSEL, pCmd->IOSelect); in XSPI_ConfigCmd()
3188 ccr_reg = &(hxspi->Instance->WCCR); in XSPI_ConfigCmd()
3189 tcr_reg = &(hxspi->Instance->WTCR); in XSPI_ConfigCmd()
3190 ir_reg = &(hxspi->Instance->WIR); in XSPI_ConfigCmd()
3191 abr_reg = &(hxspi->Instance->WABR); in XSPI_ConfigCmd()
3195 ccr_reg = &(hxspi->Instance->WPCCR); in XSPI_ConfigCmd()
3196 tcr_reg = &(hxspi->Instance->WPTCR); in XSPI_ConfigCmd()
3197 ir_reg = &(hxspi->Instance->WPIR); in XSPI_ConfigCmd()
3198 abr_reg = &(hxspi->Instance->WPABR); in XSPI_ConfigCmd()
3202 ccr_reg = &(hxspi->Instance->CCR); in XSPI_ConfigCmd()
3203 tcr_reg = &(hxspi->Instance->TCR); in XSPI_ConfigCmd()
3204 ir_reg = &(hxspi->Instance->IR); in XSPI_ConfigCmd()
3205 abr_reg = &(hxspi->Instance->ABR); in XSPI_ConfigCmd()
3229 hxspi->Instance->DLR = (pCmd->DataLength - 1U); in XSPI_ConfigCmd()
3239 CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); in XSPI_ConfigCmd()
3241 else if(hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) in XSPI_ConfigCmd()
3244 SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); in XSPI_ConfigCmd()
3279 if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && in XSPI_ConfigCmd()
3289 hxspi->Instance->AR = pCmd->Address; in XSPI_ConfigCmd()
3312 if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && in XSPI_ConfigCmd()
3348 hxspi->Instance->AR = pCmd->Address; in XSPI_ConfigCmd()
3354 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in XSPI_ConfigCmd()