Lines Matching refs:hsram
173 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, in HAL_SRAM_Init() argument
177 if (hsram == NULL) in HAL_SRAM_Init()
182 if (hsram->State == HAL_SRAM_STATE_RESET) in HAL_SRAM_Init()
185 hsram->Lock = HAL_UNLOCKED; in HAL_SRAM_Init()
188 if (hsram->MspInitCallback == NULL) in HAL_SRAM_Init()
190 hsram->MspInitCallback = HAL_SRAM_MspInit; in HAL_SRAM_Init()
192 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; in HAL_SRAM_Init()
193 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; in HAL_SRAM_Init()
196 hsram->MspInitCallback(hsram); in HAL_SRAM_Init()
199 HAL_SRAM_MspInit(hsram); in HAL_SRAM_Init()
204 (void)FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); in HAL_SRAM_Init()
207 (void)FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); in HAL_SRAM_Init()
210 (void)FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, in HAL_SRAM_Init()
211 hsram->Init.ExtendedMode); in HAL_SRAM_Init()
214 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_Init()
220 hsram->State = HAL_SRAM_STATE_READY; in HAL_SRAM_Init()
231 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) in HAL_SRAM_DeInit() argument
234 if (hsram->MspDeInitCallback == NULL) in HAL_SRAM_DeInit()
236 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; in HAL_SRAM_DeInit()
240 hsram->MspDeInitCallback(hsram); in HAL_SRAM_DeInit()
243 HAL_SRAM_MspDeInit(hsram); in HAL_SRAM_DeInit()
247 (void)FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); in HAL_SRAM_DeInit()
250 hsram->State = HAL_SRAM_STATE_RESET; in HAL_SRAM_DeInit()
253 __HAL_UNLOCK(hsram); in HAL_SRAM_DeInit()
264 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) in HAL_SRAM_MspInit() argument
267 UNUSED(hsram); in HAL_SRAM_MspInit()
280 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) in HAL_SRAM_MspDeInit() argument
283 UNUSED(hsram); in HAL_SRAM_MspDeInit()
349 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuff… in HAL_SRAM_Read_8b() argument
355 HAL_SRAM_StateTypeDef state = hsram->State; in HAL_SRAM_Read_8b()
361 __HAL_LOCK(hsram); in HAL_SRAM_Read_8b()
364 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_Read_8b()
375 hsram->State = state; in HAL_SRAM_Read_8b()
378 __HAL_UNLOCK(hsram); in HAL_SRAM_Read_8b()
397 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuf… in HAL_SRAM_Write_8b() argument
405 if (hsram->State == HAL_SRAM_STATE_READY) in HAL_SRAM_Write_8b()
408 __HAL_LOCK(hsram); in HAL_SRAM_Write_8b()
411 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_Write_8b()
422 hsram->State = HAL_SRAM_STATE_READY; in HAL_SRAM_Write_8b()
425 __HAL_UNLOCK(hsram); in HAL_SRAM_Write_8b()
444 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBu… in HAL_SRAM_Read_16b() argument
451 HAL_SRAM_StateTypeDef state = hsram->State; in HAL_SRAM_Read_16b()
457 __HAL_LOCK(hsram); in HAL_SRAM_Read_16b()
460 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_Read_16b()
482 hsram->State = state; in HAL_SRAM_Read_16b()
485 __HAL_UNLOCK(hsram); in HAL_SRAM_Read_16b()
504 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcB… in HAL_SRAM_Write_16b() argument
513 if (hsram->State == HAL_SRAM_STATE_READY) in HAL_SRAM_Write_16b()
516 __HAL_LOCK(hsram); in HAL_SRAM_Write_16b()
519 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_Write_16b()
541 hsram->State = HAL_SRAM_STATE_READY; in HAL_SRAM_Write_16b()
544 __HAL_UNLOCK(hsram); in HAL_SRAM_Write_16b()
563 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBu… in HAL_SRAM_Read_32b() argument
569 HAL_SRAM_StateTypeDef state = hsram->State; in HAL_SRAM_Read_32b()
575 __HAL_LOCK(hsram); in HAL_SRAM_Read_32b()
578 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_Read_32b()
589 hsram->State = state; in HAL_SRAM_Read_32b()
592 __HAL_UNLOCK(hsram); in HAL_SRAM_Read_32b()
611 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcB… in HAL_SRAM_Write_32b() argument
619 if (hsram->State == HAL_SRAM_STATE_READY) in HAL_SRAM_Write_32b()
622 __HAL_LOCK(hsram); in HAL_SRAM_Write_32b()
625 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_Write_32b()
636 hsram->State = HAL_SRAM_STATE_READY; in HAL_SRAM_Write_32b()
639 __HAL_UNLOCK(hsram); in HAL_SRAM_Write_32b()
658 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBu… in HAL_SRAM_Read_DMA() argument
662 HAL_SRAM_StateTypeDef state = hsram->State; in HAL_SRAM_Read_DMA()
670 __HAL_LOCK(hsram); in HAL_SRAM_Read_DMA()
673 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_Read_DMA()
678 hsram->hdma->XferCpltCallback = SRAM_DMACplt; in HAL_SRAM_Read_DMA()
682 hsram->hdma->XferCpltCallback = SRAM_DMACpltProt; in HAL_SRAM_Read_DMA()
684 hsram->hdma->XferErrorCallback = SRAM_DMAError; in HAL_SRAM_Read_DMA()
686 if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_SRAM_Read_DMA()
688 if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U)) in HAL_SRAM_Read_DMA()
691 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Read_DMA()
707 hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size; in HAL_SRAM_Read_DMA()
709 … hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pAddress; in HAL_SRAM_Read_DMA()
711 …hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pDstBuffer; in HAL_SRAM_Read_DMA()
714 status = HAL_DMAEx_List_Start_IT(hsram->hdma); in HAL_SRAM_Read_DMA()
719 hsram->State = HAL_SRAM_STATE_READY; in HAL_SRAM_Read_DMA()
721 __HAL_UNLOCK(hsram); in HAL_SRAM_Read_DMA()
729 data_width = hsram->hdma->Init.DestDataWidth; in HAL_SRAM_Read_DMA()
745 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, size); in HAL_SRAM_Read_DMA()
749 __HAL_UNLOCK(hsram); in HAL_SRAM_Read_DMA()
768 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcB… in HAL_SRAM_Write_DMA() argument
776 if (hsram->State == HAL_SRAM_STATE_READY) in HAL_SRAM_Write_DMA()
779 __HAL_LOCK(hsram); in HAL_SRAM_Write_DMA()
782 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_Write_DMA()
785 hsram->hdma->XferCpltCallback = SRAM_DMACplt; in HAL_SRAM_Write_DMA()
786 hsram->hdma->XferErrorCallback = SRAM_DMAError; in HAL_SRAM_Write_DMA()
788 if ((hsram->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_SRAM_Write_DMA()
790 if ((hsram->hdma->LinkedListQueue != 0U) && (hsram->hdma->LinkedListQueue->Head != 0U)) in HAL_SRAM_Write_DMA()
793 …data_width = hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR… in HAL_SRAM_Write_DMA()
809 hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = size; in HAL_SRAM_Write_DMA()
811 …hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pSrcBuffer; in HAL_SRAM_Write_DMA()
813 … hsram->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pAddress; in HAL_SRAM_Write_DMA()
815 status = HAL_DMAEx_List_Start_IT(hsram->hdma); in HAL_SRAM_Write_DMA()
820 hsram->State = HAL_SRAM_STATE_READY; in HAL_SRAM_Write_DMA()
822 __HAL_UNLOCK(hsram); in HAL_SRAM_Write_DMA()
830 data_width = hsram->hdma->Init.DestDataWidth; in HAL_SRAM_Write_DMA()
846 status = HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, size); in HAL_SRAM_Write_DMA()
850 __HAL_UNLOCK(hsram); in HAL_SRAM_Write_DMA()
872 HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef C… in HAL_SRAM_RegisterCallback() argument
883 state = hsram->State; in HAL_SRAM_RegisterCallback()
889 hsram->MspInitCallback = pCallback; in HAL_SRAM_RegisterCallback()
892 hsram->MspDeInitCallback = pCallback; in HAL_SRAM_RegisterCallback()
921 HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef… in HAL_SRAM_UnRegisterCallback() argument
926 state = hsram->State; in HAL_SRAM_UnRegisterCallback()
932 hsram->MspInitCallback = HAL_SRAM_MspInit; in HAL_SRAM_UnRegisterCallback()
935 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; in HAL_SRAM_UnRegisterCallback()
938 hsram->DmaXferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; in HAL_SRAM_UnRegisterCallback()
941 hsram->DmaXferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; in HAL_SRAM_UnRegisterCallback()
954 hsram->MspInitCallback = HAL_SRAM_MspInit; in HAL_SRAM_UnRegisterCallback()
957 hsram->MspDeInitCallback = HAL_SRAM_MspDeInit; in HAL_SRAM_UnRegisterCallback()
985 HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDe… in HAL_SRAM_RegisterDmaCallback() argument
997 __HAL_LOCK(hsram); in HAL_SRAM_RegisterDmaCallback()
999 state = hsram->State; in HAL_SRAM_RegisterDmaCallback()
1005 hsram->DmaXferCpltCallback = pCallback; in HAL_SRAM_RegisterDmaCallback()
1008 hsram->DmaXferErrorCallback = pCallback; in HAL_SRAM_RegisterDmaCallback()
1023 __HAL_UNLOCK(hsram); in HAL_SRAM_RegisterDmaCallback()
1053 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) in HAL_SRAM_WriteOperation_Enable() argument
1056 if (hsram->State == HAL_SRAM_STATE_PROTECTED) in HAL_SRAM_WriteOperation_Enable()
1059 __HAL_LOCK(hsram); in HAL_SRAM_WriteOperation_Enable()
1062 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_WriteOperation_Enable()
1065 (void)FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Enable()
1068 hsram->State = HAL_SRAM_STATE_READY; in HAL_SRAM_WriteOperation_Enable()
1071 __HAL_UNLOCK(hsram); in HAL_SRAM_WriteOperation_Enable()
1087 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) in HAL_SRAM_WriteOperation_Disable() argument
1090 if (hsram->State == HAL_SRAM_STATE_READY) in HAL_SRAM_WriteOperation_Disable()
1093 __HAL_LOCK(hsram); in HAL_SRAM_WriteOperation_Disable()
1096 hsram->State = HAL_SRAM_STATE_BUSY; in HAL_SRAM_WriteOperation_Disable()
1099 (void)FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); in HAL_SRAM_WriteOperation_Disable()
1102 hsram->State = HAL_SRAM_STATE_PROTECTED; in HAL_SRAM_WriteOperation_Disable()
1105 __HAL_UNLOCK(hsram); in HAL_SRAM_WriteOperation_Disable()
1140 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) in HAL_SRAM_GetState() argument
1142 return hsram->State; in HAL_SRAM_GetState()
1165 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); in SRAM_DMACplt() local
1171 hsram->State = HAL_SRAM_STATE_READY; in SRAM_DMACplt()
1174 hsram->DmaXferCpltCallback(hdma); in SRAM_DMACplt()
1188 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); in SRAM_DMACpltProt() local
1194 hsram->State = HAL_SRAM_STATE_PROTECTED; in SRAM_DMACpltProt()
1197 hsram->DmaXferCpltCallback(hdma); in SRAM_DMACpltProt()
1211 SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); in SRAM_DMAError() local
1217 hsram->State = HAL_SRAM_STATE_ERROR; in SRAM_DMAError()
1220 hsram->DmaXferErrorCallback(hdma); in SRAM_DMAError()