Lines Matching refs:PLLCKSELR

374   WRITE_REG(RCC->PLLCKSELR, 0x02020200U);  in HAL_RCC_DeInit()
1293       pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);  in HAL_RCC_GetSysClockFreq()
1294       pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos)  ;  in HAL_RCC_GetSysClockFreq()
1713   regvalue = RCC->PLLCKSELR;  in HAL_RCC_GetOscConfig()
1752   regvalue = RCC->PLLCKSELR;  in HAL_RCC_GetOscConfig()
1791   regvalue = RCC->PLLCKSELR;  in HAL_RCC_GetOscConfig()
2025 …MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | (RCC_PLLCKSELR_DIVM1 << ((RCC_PLLCKSELR_DIVM2_P…  in RCC_PLL_Config()
2028     if ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) != pllsrc)  in RCC_PLL_Config()
2082 …MODIFY_REG(RCC->PLLCKSELR, ((RCC_PLLCKSELR_DIVM1 << (RCC_PLLCKSELR_DIVM1_Pos + ((RCC_PLLCKSELR_DIV…  in RCC_PLL_Config()
2104   tmpreg1 = RCC->PLLCKSELR;  in RCC_PLL1_GetVCOOutputFreq()
2179   tmpreg1 = RCC->PLLCKSELR;  in RCC_PLL2_GetVCOOutputFreq()
2254   tmpreg1 = RCC->PLLCKSELR;  in RCC_PLL3_GetVCOOutputFreq()