Lines Matching refs:PWR
34 #if defined (PWR)
258 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
265 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
289 SET_BIT(PWR->CR1, PWR_CR1_PVDE); in LL_PWR_EnablePVD()
299 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE); in LL_PWR_DisablePVD()
309 return ((READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
328 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel); in LL_PWR_SetPVDLevel()
346 return READ_BIT(PWR->CR1, PWR_CR1_PLS); in LL_PWR_GetPVDLevel()
356 SET_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_EnableBkUpAccess()
366 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_DisableBkUpAccess()
376 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
386 SET_BIT(PWR->CR1, PWR_CR1_FLPS); in LL_PWR_EnableFlashLowPower()
396 CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS); in LL_PWR_DisableFlashLowPower()
406 return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL); in LL_PWR_IsEnabledFlashLowPower()
416 SET_BIT(PWR->CR1, PWR_CR1_BOOSTE); in LL_PWR_EnableAnalogBooster()
426 CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE); in LL_PWR_DisableAnalogBooster()
436 return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL); in LL_PWR_IsEnabledAnalogBooster()
446 SET_BIT(PWR->CR1, PWR_CR1_AVDREADY); in LL_PWR_EnableAnalogVoltageReady()
456 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDREADY); in LL_PWR_DisableAnalogVoltageReady()
466 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDREADY) == (PWR_CR1_AVDREADY)) ? 1UL : 0UL); in LL_PWR_IsEnabledAnalogVoltageReady()
476 SET_BIT(PWR->CR1, PWR_CR1_AVDEN); in LL_PWR_EnableAVD()
486 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN); in LL_PWR_DisableAVD()
496 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledAVD()
511 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel); in LL_PWR_SetAVDLevel()
525 return READ_BIT(PWR->CR1, PWR_CR1_ALS); in LL_PWR_GetAVDLevel()
540 SET_BIT(PWR->CSR1, PWR_CSR1_BREN); in LL_PWR_EnableBkUpRegulator()
550 CLEAR_BIT(PWR->CSR1, PWR_CSR1_BREN); in LL_PWR_DisableBkUpRegulator()
560 return ((READ_BIT(PWR->CSR1, PWR_CSR1_BREN) == (PWR_CSR1_BREN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpRegulator()
570 SET_BIT(PWR->CSR1, PWR_CSR1_MONEN); in LL_PWR_EnableMonitoring()
580 CLEAR_BIT(PWR->CSR1, PWR_CSR1_MONEN); in LL_PWR_DisableMonitoring()
590 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MONEN) == (PWR_CSR1_MONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledMonitoring()
612 …MODIFY_REG(PWR->CSR2, (PWR_CSR2_SDHILEVEL | PWR_CSR2_SMPSEXTHP | PWR_CSR2_SDEN | PWR_CSR2_LDOEN | … in LL_PWR_ConfigSupply()
634 return READ_BIT(PWR->CSR2, in LL_PWR_GetSupply()
645 SET_BIT(PWR->CSR2, PWR_CSR2_VBE); in LL_PWR_EnableBatteryCharging()
655 CLEAR_BIT(PWR->CSR2, PWR_CSR2_VBE); in LL_PWR_DisableBatteryCharging()
665 return ((READ_BIT(PWR->CSR2, PWR_CSR2_VBE) == (PWR_CSR2_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
678 MODIFY_REG(PWR->CSR2, PWR_CSR2_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
690 return (READ_BIT(PWR->CSR2, PWR_CSR2_VBRS)); in LL_PWR_GetBattChargResistor()
705 MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP1, Capacitor); in LL_PWR_SetXSPI1Capacitor()
719 return (READ_BIT(PWR->CSR2, PWR_CSR2_XSPICAP1)); in LL_PWR_GetXSPI1Capacitor()
734 MODIFY_REG(PWR->CSR2, PWR_CSR2_XSPICAP2, Capacitor); in LL_PWR_SetXSPI2Capacitor()
748 return (uint32_t)(READ_BIT(PWR->CSR2, PWR_CSR2_XSPICAP2)); in LL_PWR_GetXSPI2Capacitor()
758 SET_BIT(PWR->CSR2, PWR_CSR2_USB33DEN); in LL_PWR_EnableUSBVoltageDetector()
768 CLEAR_BIT(PWR->CSR2, PWR_CSR2_USB33DEN); in LL_PWR_DisableUSBVoltageDetector()
778 return ((READ_BIT(PWR->CSR2, PWR_CSR2_USB33DEN) == (PWR_CSR2_USB33DEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUSBVoltageDetector()
788 SET_BIT(PWR->CSR2, PWR_CSR2_USBREGEN); in LL_PWR_EnableUSBReg()
798 CLEAR_BIT(PWR->CSR2, PWR_CSR2_USBREGEN); in LL_PWR_DisableUSBReg()
808 return ((READ_BIT(PWR->CSR2, PWR_CSR2_USBREGEN) == (PWR_CSR2_USBREGEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUSBReg()
818 SET_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN); in LL_PWR_EnableUSBHSPHYReg()
828 CLEAR_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN); in LL_PWR_DisableUSBHSPHYReg()
838 return ((READ_BIT(PWR->CSR2, PWR_CSR2_USBHSREGEN) == (PWR_CSR2_USBHSREGEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUSBHSPHYReg()
850 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); in LL_PWR_EnableUCPDStandbyMode()
862 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); in LL_PWR_DisableUCPDStandbyMode()
872 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY) == (PWR_UCPDR_UCPD_STBY)) ? 1UL : 0UL); in LL_PWR_IsEnabledUCPDStandbyMode()
882 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); in LL_PWR_EnableUCPDDeadBattery()
892 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); in LL_PWR_DisableUCPDDeadBattery()
902 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 1UL : 0UL); in LL_PWR_IsEnabledUCPDDeadBattery()
912 SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1); in LL_PWR_EnableXSPIM1()
922 CLEAR_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1); in LL_PWR_DisableXSPIM1()
932 return ((READ_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM1) == (PWR_CSR2_EN_XSPIM1)) ? 1UL : 0UL); in LL_PWR_IsEnabledXSPIM1()
942 SET_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2); in LL_PWR_EnableXSPIM2()
952 CLEAR_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2); in LL_PWR_DisableXSPIM2()
962 return ((READ_BIT(PWR->CSR2, PWR_CSR2_EN_XSPIM2) == (PWR_CSR2_EN_XSPIM2)) ? 1UL : 0UL); in LL_PWR_IsEnabledXSPIM2()
975 MODIFY_REG(PWR->CSR3, PWR_CSR3_PDDS, PDMode); in LL_PWR_SetPowerDownModeDS()
987 return (uint32_t)(READ_BIT(PWR->CSR3, PWR_CSR3_PDDS)); in LL_PWR_GetPowerDownModeDS()
1000 MODIFY_REG(PWR->CSR4, PWR_CSR4_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
1012 return (uint32_t)(READ_BIT(PWR->CSR4, PWR_CSR4_VOS)); in LL_PWR_GetRegulVoltageScaling()
1025 MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling); in LL_PWR_SetStopModeRegulVoltageScaling()
1037 return READ_BIT(PWR->CR1, PWR_CR1_SVOS); in LL_PWR_GetStopModeRegulVoltageScaling()
1055 SET_BIT(PWR->WKUPEPR, WakeUpPin); in LL_PWR_EnableWakeUpPin()
1073 CLEAR_BIT(PWR->WKUPEPR, WakeUpPin); in LL_PWR_DisableWakeUpPin()
1091 return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
1109 SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); in LL_PWR_SetWakeUpPinPolarityLow()
1127 CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)); in LL_PWR_SetWakeUpPinPolarityHigh()
1145 …return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEP… in LL_PWR_IsWakeUpPinPolarityLow()
1163 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullNone()
1183 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullUp()
1203 MODIFY_REG(PWR->WKUPEPR, \ in LL_PWR_SetWakeUpPinPullDown()
1226 …uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHI… in LL_PWR_GetWakeUpPinPull()
1238 SET_BIT(PWR->APCR, PWR_APCR_I3CPB6_PU); in LL_PWR_EnableI3CPB6PU()
1248 CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB6_PU); in LL_PWR_DisableI3CPB6PU()
1258 return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB6_PU) == (PWR_APCR_I3CPB6_PU)) ? 1UL : 0UL); in LL_PWR_IsEnabledI3CPB6PU()
1268 SET_BIT(PWR->APCR, PWR_APCR_I3CPB7_PU); in LL_PWR_EnableI3CPB7PU()
1278 CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB7_PU); in LL_PWR_DisableI3CPB7PU()
1288 return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB7_PU) == (PWR_APCR_I3CPB7_PU)) ? 1UL : 0UL); in LL_PWR_IsEnabledI3CPB7PU()
1298 SET_BIT(PWR->APCR, PWR_APCR_I3CPB8_PU); in LL_PWR_EnableI3CPB8PU()
1308 CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB8_PU); in LL_PWR_DisableI3CPB8PU()
1318 return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB8_PU) == (PWR_APCR_I3CPB8_PU)) ? 1UL : 0UL); in LL_PWR_IsEnabledI3CPB8PU()
1328 SET_BIT(PWR->APCR, PWR_APCR_I3CPB9_PU); in LL_PWR_EnableI3CPB9PU()
1338 CLEAR_BIT(PWR->APCR, PWR_APCR_I3CPB9_PU); in LL_PWR_DisableI3CPB9PU()
1348 return ((READ_BIT(PWR->APCR, PWR_APCR_I3CPB9_PU) == (PWR_APCR_I3CPB9_PU)) ? 1UL : 0UL); in LL_PWR_IsEnabledI3CPB9PU()
1358 SET_BIT(PWR->APCR, PWR_APCR_APC); in LL_PWR_EnablePUPDConfig()
1368 CLEAR_BIT(PWR->APCR, PWR_APCR_APC); in LL_PWR_DisablePUPDConfig()
1378 return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL); in LL_PWR_IsEnabledPUPDConfig()
1392 SET_BIT(PWR->PUCRN, GPIOPin); in LL_PWR_EnableGPIONPullUp()
1406 CLEAR_BIT(PWR->PUCRN, GPIOPin); in LL_PWR_DisableGPIONPullUp()
1420 return ((READ_BIT(PWR->PUCRN, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledGPIONPullUp()
1435 SET_BIT(PWR->PUCRO, GPIOPin); in LL_PWR_EnableGPIOOPullUp()
1449 CLEAR_BIT(PWR->PUCRO, GPIOPin); in LL_PWR_DisableGPIOOPullUp()
1463 return ((READ_BIT(PWR->PUCRO, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledGPIOOPullUp()
1480 SET_BIT(PWR->PDCRN, GPIOPin); in LL_PWR_EnableGPIONPullDown()
1497 CLEAR_BIT(PWR->PDCRN, GPIOPin); in LL_PWR_DisableGPIONPullDown()
1514 return ((READ_BIT(PWR->PDCRN, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledGPIONPullDown()
1529 SET_BIT(PWR->PDCRO, GPIOPin); in LL_PWR_EnableGPIOOPullDown()
1545 CLEAR_BIT(PWR->PDCRO, GPIOPin); in LL_PWR_DisableGPIOOPullDown()
1561 return ((READ_BIT(PWR->PDCRO, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledGPIOOPullDown()
1576 SET_BIT(PWR->PDCRP, GPIOPin); in LL_PWR_EnableGPIOPPullDown()
1591 CLEAR_BIT(PWR->PDCRP, GPIOPin); in LL_PWR_DisableGPIOPPullDown()
1606 return ((READ_BIT(PWR->PDCRP, GPIOPin) == (GPIOPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledGPIOPPullDown()
1624 return ((READ_BIT(PWR->SR1, PWR_SR1_ACTVOSRDY) == (PWR_SR1_ACTVOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_ACTVOSRDY()
1634 return ((READ_BIT(PWR->SR1, PWR_SR1_PVDO) == (PWR_SR1_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1644 return ((READ_BIT(PWR->SR1, PWR_SR1_AVDO) == (PWR_SR1_AVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_AVDO()
1654 return ((READ_BIT(PWR->CSR1, PWR_CSR1_BRRDY) == (PWR_CSR1_BRRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_BRRDY()
1664 return ((READ_BIT(PWR->CSR1, PWR_CSR1_VBATL) == (PWR_CSR1_VBATL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATL()
1674 return ((READ_BIT(PWR->CSR1, PWR_CSR1_VBATH) == (PWR_CSR1_VBATH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATH()
1684 return ((READ_BIT(PWR->CSR1, PWR_CSR1_TEMPL) == (PWR_CSR1_TEMPL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPL()
1694 return ((READ_BIT(PWR->CSR1, PWR_CSR1_TEMPH) == (PWR_CSR1_TEMPH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPH()
1704 return ((READ_BIT(PWR->CSR2, PWR_CSR2_SDEXTRDY) == (PWR_CSR2_SDEXTRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SDEXTRDY()
1714 return ((READ_BIT(PWR->CSR2, PWR_CSR2_USB33RDY) == (PWR_CSR2_USB33RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_USB33RDY()
1724 return ((READ_BIT(PWR->CSR3, PWR_CSR3_STOPF) == (PWR_CSR3_STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_STOP()
1734 return ((READ_BIT(PWR->CSR3, PWR_CSR3_SBF) == (PWR_CSR3_SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
1745 return ((READ_BIT(PWR->CSR4, PWR_CSR4_VOSRDY) == (PWR_CSR4_VOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOSRDY()
1755 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
1765 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1775 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1785 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
1795 SET_BIT(PWR->CSR3, PWR_CSR3_CSSF); in LL_PWR_ClearFlag_STOP_SB()
1805 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1); in LL_PWR_ClearFlag_WU1()
1815 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2); in LL_PWR_ClearFlag_WU2()
1825 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3); in LL_PWR_ClearFlag_WU3()
1835 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4); in LL_PWR_ClearFlag_WU4()
1845 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC); in LL_PWR_ClearFlag_WU()