322 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB1_GRP1_EnableClock()  argument
325   SET_BIT(RCC->AHB1ENR, Periphs);  in LL_AHB1_GRP1_EnableClock()
327   tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);  in LL_AHB1_GRP1_EnableClock()
354 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB1_GRP1_IsEnabledClock()  argument
356   return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1U : 0U);  in LL_AHB1_GRP1_IsEnabledClock()
382 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB1_GRP1_DisableClock()  argument
384   CLEAR_BIT(RCC->AHB1ENR, Periphs);  in LL_AHB1_GRP1_DisableClock()
406 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB1_GRP1_ForceReset()  argument
408   SET_BIT(RCC->AHB1RSTR, Periphs);  in LL_AHB1_GRP1_ForceReset()
430 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB1_GRP1_ReleaseReset()  argument
432   CLEAR_BIT(RCC->AHB1RSTR, Periphs);  in LL_AHB1_GRP1_ReleaseReset()
458 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB1_GRP1_EnableClockSleep()  argument
461   SET_BIT(RCC->AHB1LPENR, Periphs);  in LL_AHB1_GRP1_EnableClockSleep()
463   tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);  in LL_AHB1_GRP1_EnableClockSleep()
490 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB1_GRP1_DisableClockSleep()  argument
492   CLEAR_BIT(RCC->AHB1LPENR, Periphs);  in LL_AHB1_GRP1_DisableClockSleep()
518 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB2_GRP1_EnableClock()  argument
521   SET_BIT(RCC->AHB2ENR, Periphs);  in LL_AHB2_GRP1_EnableClock()
523   tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);  in LL_AHB2_GRP1_EnableClock()
542 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB2_GRP1_IsEnabledClock()  argument
544   return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs) ? 1U : 0U);  in LL_AHB2_GRP1_IsEnabledClock()
562 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB2_GRP1_DisableClock()  argument
564   CLEAR_BIT(RCC->AHB2ENR, Periphs);  in LL_AHB2_GRP1_DisableClock()
578 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB2_GRP1_ForceReset()  argument
580   SET_BIT(RCC->AHB2RSTR, Periphs);  in LL_AHB2_GRP1_ForceReset()
594 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB2_GRP1_ReleaseReset()  argument
596   CLEAR_BIT(RCC->AHB2RSTR, Periphs);  in LL_AHB2_GRP1_ReleaseReset()
614 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB2_GRP1_EnableClockSleep()  argument
617   SET_BIT(RCC->AHB2LPENR, Periphs);  in LL_AHB2_GRP1_EnableClockSleep()
619   tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);  in LL_AHB2_GRP1_EnableClockSleep()
638 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB2_GRP1_DisableClockSleep()  argument
640   CLEAR_BIT(RCC->AHB2LPENR, Periphs);  in LL_AHB2_GRP1_DisableClockSleep()
668 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB3_GRP1_EnableClock()  argument
671   SET_BIT(RCC->AHB3ENR, Periphs);  in LL_AHB3_GRP1_EnableClock()
673   tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);  in LL_AHB3_GRP1_EnableClock()
694 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB3_GRP1_IsEnabledClock()  argument
696   return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1U : 0U);  in LL_AHB3_GRP1_IsEnabledClock()
716 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB3_GRP1_DisableClock()  argument
718   CLEAR_BIT(RCC->AHB3ENR, Periphs);  in LL_AHB3_GRP1_DisableClock()
738 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB3_GRP1_ForceReset()  argument
740   SET_BIT(RCC->AHB3RSTR, Periphs);  in LL_AHB3_GRP1_ForceReset()
760 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB3_GRP1_ReleaseReset()  argument
762   CLEAR_BIT(RCC->AHB3RSTR, Periphs);  in LL_AHB3_GRP1_ReleaseReset()
782 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB3_GRP1_EnableClockSleep()  argument
785   SET_BIT(RCC->AHB3LPENR, Periphs);  in LL_AHB3_GRP1_EnableClockSleep()
787   tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);  in LL_AHB3_GRP1_EnableClockSleep()
808 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB3_GRP1_DisableClockSleep()  argument
810   CLEAR_BIT(RCC->AHB3LPENR, Periphs);  in LL_AHB3_GRP1_DisableClockSleep()
854 __STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB4_GRP1_EnableClock()  argument
857   SET_BIT(RCC->AHB4ENR, Periphs);  in LL_AHB4_GRP1_EnableClock()
859   tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);  in LL_AHB4_GRP1_EnableClock()
896 __STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB4_GRP1_IsEnabledClock()  argument
898   return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs) ? 1U : 0U);  in LL_AHB4_GRP1_IsEnabledClock()
934 __STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB4_GRP1_DisableClock()  argument
936   CLEAR_BIT(RCC->AHB4ENR, Periphs);  in LL_AHB4_GRP1_DisableClock()
972 __STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB4_GRP1_ForceReset()  argument
974   SET_BIT(RCC->AHB4RSTR, Periphs);  in LL_AHB4_GRP1_ForceReset()
1008 __STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB4_GRP1_ReleaseReset()  argument
1010   CLEAR_BIT(RCC->AHB4RSTR, Periphs);  in LL_AHB4_GRP1_ReleaseReset()
1046 __STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB4_GRP1_EnableClockSleep()  argument
1049   SET_BIT(RCC->AHB4LPENR, Periphs);  in LL_AHB4_GRP1_EnableClockSleep()
1051   tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);  in LL_AHB4_GRP1_EnableClockSleep()
1088 __STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB4_GRP1_DisableClockSleep()  argument
1090   CLEAR_BIT(RCC->AHB4LPENR, Periphs);  in LL_AHB4_GRP1_DisableClockSleep()
1128 __STATIC_INLINE void LL_AHB5_GRP1_EnableClock(uint32_t Periphs)  in LL_AHB5_GRP1_EnableClock()  argument
1131   SET_BIT(RCC->AHB5ENR, Periphs);  in LL_AHB5_GRP1_EnableClock()
1133   tmpreg = READ_BIT(RCC->AHB5ENR, Periphs);  in LL_AHB5_GRP1_EnableClock()
1164 __STATIC_INLINE uint32_t LL_AHB5_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_AHB5_GRP1_IsEnabledClock()  argument
1166   return ((READ_BIT(RCC->AHB5ENR, Periphs) == Periphs) ? 1U : 0U);  in LL_AHB5_GRP1_IsEnabledClock()
1196 __STATIC_INLINE void LL_AHB5_GRP1_DisableClock(uint32_t Periphs)  in LL_AHB5_GRP1_DisableClock()  argument
1198   CLEAR_BIT(RCC->AHB5ENR, Periphs);  in LL_AHB5_GRP1_DisableClock()
1228 __STATIC_INLINE void LL_AHB5_GRP1_ForceReset(uint32_t Periphs)  in LL_AHB5_GRP1_ForceReset()  argument
1230   SET_BIT(RCC->AHB5RSTR, Periphs);  in LL_AHB5_GRP1_ForceReset()
1260 __STATIC_INLINE void LL_AHB5_GRP1_ReleaseReset(uint32_t Periphs)  in LL_AHB5_GRP1_ReleaseReset()  argument
1262   CLEAR_BIT(RCC->AHB5RSTR, Periphs);  in LL_AHB5_GRP1_ReleaseReset()
1301 __STATIC_INLINE void LL_AHB5_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_AHB5_GRP1_EnableClockSleep()  argument
1304   SET_BIT(RCC->AHB5LPENR, Periphs);  in LL_AHB5_GRP1_EnableClockSleep()
1306   tmpreg = READ_BIT(RCC->AHB5LPENR, Periphs);  in LL_AHB5_GRP1_EnableClockSleep()
1347 __STATIC_INLINE void LL_AHB5_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_AHB5_GRP1_DisableClockSleep()  argument
1349   CLEAR_BIT(RCC->AHB5LPENR, Periphs);  in LL_AHB5_GRP1_DisableClockSleep()
1415 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)  in LL_APB1_GRP1_EnableClock()  argument
1418   SET_BIT(RCC->APB1ENR1, Periphs);  in LL_APB1_GRP1_EnableClock()
1420   tmpreg = READ_BIT(RCC->APB1ENR1, Periphs);  in LL_APB1_GRP1_EnableClock()
1479 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_APB1_GRP1_IsEnabledClock()  argument
1481   return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1U : 0U);  in LL_APB1_GRP1_IsEnabledClock()
1537 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)  in LL_APB1_GRP1_DisableClock()  argument
1539   CLEAR_BIT(RCC->APB1ENR1, Periphs);  in LL_APB1_GRP1_DisableClock()
1597 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)  in LL_APB1_GRP1_ForceReset()  argument
1599   SET_BIT(RCC->APB1RSTR1, Periphs);  in LL_APB1_GRP1_ForceReset()
1657 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)  in LL_APB1_GRP1_ReleaseReset()  argument
1659   CLEAR_BIT(RCC->APB1RSTR1, Periphs);  in LL_APB1_GRP1_ReleaseReset()
1718 __STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_APB1_GRP1_EnableClockSleep()  argument
1721   SET_BIT(RCC->APB1LPENR1, Periphs);  in LL_APB1_GRP1_EnableClockSleep()
1723   tmpreg = READ_BIT(RCC->APB1LPENR1, Periphs);  in LL_APB1_GRP1_EnableClockSleep()
1782 __STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_APB1_GRP1_DisableClockSleep()  argument
1784   CLEAR_BIT(RCC->APB1LPENR1, Periphs);  in LL_APB1_GRP1_DisableClockSleep()
1800 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)  in LL_APB1_GRP2_EnableClock()  argument
1803   SET_BIT(RCC->APB1ENR2, Periphs);  in LL_APB1_GRP2_EnableClock()
1805   tmpreg = READ_BIT(RCC->APB1ENR2, Periphs);  in LL_APB1_GRP2_EnableClock()
1822 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)  in LL_APB1_GRP2_IsEnabledClock()  argument
1824   return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1U : 0U);  in LL_APB1_GRP2_IsEnabledClock()
1840 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)  in LL_APB1_GRP2_DisableClock()  argument
1842   CLEAR_BIT(RCC->APB1ENR2, Periphs);  in LL_APB1_GRP2_DisableClock()
1858 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)  in LL_APB1_GRP2_ForceReset()  argument
1860   SET_BIT(RCC->APB1RSTR2, Periphs);  in LL_APB1_GRP2_ForceReset()
1876 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)  in LL_APB1_GRP2_ReleaseReset()  argument
1878   CLEAR_BIT(RCC->APB1RSTR2, Periphs);  in LL_APB1_GRP2_ReleaseReset()
1894 __STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)  in LL_APB1_GRP2_EnableClockSleep()  argument
1897   SET_BIT(RCC->APB1LPENR2, Periphs);  in LL_APB1_GRP2_EnableClockSleep()
1899   tmpreg = READ_BIT(RCC->APB1LPENR2, Periphs);  in LL_APB1_GRP2_EnableClockSleep()
1916 __STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)  in LL_APB1_GRP2_DisableClockSleep()  argument
1918   CLEAR_BIT(RCC->APB1LPENR2, Periphs);  in LL_APB1_GRP2_DisableClockSleep()
1956 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)  in LL_APB2_GRP1_EnableClock()  argument
1959   SET_BIT(RCC->APB2ENR, Periphs);  in LL_APB2_GRP1_EnableClock()
1961   tmpreg = READ_BIT(RCC->APB2ENR, Periphs);  in LL_APB2_GRP1_EnableClock()
1992 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_APB2_GRP1_IsEnabledClock()  argument
1994   return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1U : 0U);  in LL_APB2_GRP1_IsEnabledClock()
2024 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)  in LL_APB2_GRP1_DisableClock()  argument
2026   CLEAR_BIT(RCC->APB2ENR, Periphs);  in LL_APB2_GRP1_DisableClock()
2056 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)  in LL_APB2_GRP1_ForceReset()  argument
2058   SET_BIT(RCC->APB2RSTR, Periphs);  in LL_APB2_GRP1_ForceReset()
2088 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)  in LL_APB2_GRP1_ReleaseReset()  argument
2090   CLEAR_BIT(RCC->APB2RSTR, Periphs);  in LL_APB2_GRP1_ReleaseReset()
2120 __STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_APB2_GRP1_EnableClockSleep()  argument
2123   SET_BIT(RCC->APB2LPENR, Periphs);  in LL_APB2_GRP1_EnableClockSleep()
2125   tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);  in LL_APB2_GRP1_EnableClockSleep()
2156 __STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_APB2_GRP1_DisableClockSleep()  argument
2158   CLEAR_BIT(RCC->APB2LPENR, Periphs);  in LL_APB2_GRP1_DisableClockSleep()
2194 __STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)  in LL_APB4_GRP1_EnableClock()  argument
2197   SET_BIT(RCC->APB4ENR, Periphs);  in LL_APB4_GRP1_EnableClock()
2199   tmpreg = READ_BIT(RCC->APB4ENR, Periphs);  in LL_APB4_GRP1_EnableClock()
2228 __STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_APB4_GRP1_IsEnabledClock()  argument
2230   return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs) ? 1U : 0U);  in LL_APB4_GRP1_IsEnabledClock()
2258 __STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)  in LL_APB4_GRP1_DisableClock()  argument
2260   CLEAR_BIT(RCC->APB4ENR, Periphs);  in LL_APB4_GRP1_DisableClock()
2286 __STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)  in LL_APB4_GRP1_ForceReset()  argument
2288   SET_BIT(RCC->APB4RSTR, Periphs);  in LL_APB4_GRP1_ForceReset()
2314 __STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)  in LL_APB4_GRP1_ReleaseReset()  argument
2316   CLEAR_BIT(RCC->APB4RSTR, Periphs);  in LL_APB4_GRP1_ReleaseReset()
2344 __STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_APB4_GRP1_EnableClockSleep()  argument
2347   SET_BIT(RCC->APB4LPENR, Periphs);  in LL_APB4_GRP1_EnableClockSleep()
2349   tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);  in LL_APB4_GRP1_EnableClockSleep()
2378 __STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_APB4_GRP1_DisableClockSleep()  argument
2380   CLEAR_BIT(RCC->APB4LPENR, Periphs);  in LL_APB4_GRP1_DisableClockSleep()
2404 __STATIC_INLINE void LL_APB5_GRP1_EnableClock(uint32_t Periphs)  in LL_APB5_GRP1_EnableClock()  argument
2407   SET_BIT(RCC->APB5ENR, Periphs);  in LL_APB5_GRP1_EnableClock()
2409   tmpreg = READ_BIT(RCC->APB5ENR, Periphs);  in LL_APB5_GRP1_EnableClock()
2426 __STATIC_INLINE uint32_t LL_APB5_GRP1_IsEnabledClock(uint32_t Periphs)  in LL_APB5_GRP1_IsEnabledClock()  argument
2428   return ((READ_BIT(RCC->APB5ENR, Periphs) == Periphs) ? 1U : 0U);  in LL_APB5_GRP1_IsEnabledClock()
2444 __STATIC_INLINE void LL_APB5_GRP1_DisableClock(uint32_t Periphs)  in LL_APB5_GRP1_DisableClock()  argument
2446   CLEAR_BIT(RCC->APB5ENR, Periphs);  in LL_APB5_GRP1_DisableClock()
2462 __STATIC_INLINE void LL_APB5_GRP1_ForceReset(uint32_t Periphs)  in LL_APB5_GRP1_ForceReset()  argument
2464   SET_BIT(RCC->APB5RSTR, Periphs);  in LL_APB5_GRP1_ForceReset()
2480 __STATIC_INLINE void LL_APB5_GRP1_ReleaseReset(uint32_t Periphs)  in LL_APB5_GRP1_ReleaseReset()  argument
2482   CLEAR_BIT(RCC->APB5RSTR, Periphs);  in LL_APB5_GRP1_ReleaseReset()
2498 __STATIC_INLINE void LL_APB5_GRP1_EnableClockSleep(uint32_t Periphs)  in LL_APB5_GRP1_EnableClockSleep()  argument
2501   SET_BIT(RCC->APB5LPENR, Periphs);  in LL_APB5_GRP1_EnableClockSleep()
2503   tmpreg = READ_BIT(RCC->APB5LPENR, Periphs);  in LL_APB5_GRP1_EnableClockSleep()
2520 __STATIC_INLINE void LL_APB5_GRP1_DisableClockSleep(uint32_t Periphs)  in LL_APB5_GRP1_DisableClockSleep()  argument
2522   CLEAR_BIT(RCC->APB5LPENR, Periphs);  in LL_APB5_GRP1_DisableClockSleep()
2588 __STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)  in LL_CKGA_Enable()  argument
2590   CLEAR_BIT(RCC->CKGDISR, Periphs);  in LL_CKGA_Enable()
2648 __STATIC_INLINE uint32_t LL_CKGA_IsEnabledClock(uint32_t Periphs)  in LL_CKGA_IsEnabledClock()  argument
2650   return ((READ_BIT(RCC->CKGDISR, Periphs) == 0U) ? 1U : 0U);  in LL_CKGA_IsEnabledClock()
2708 __STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)  in LL_CKGA_Disable()  argument
2710   SET_BIT(RCC->CKGDISR, Periphs);  in LL_CKGA_Disable()