Lines Matching refs:APB4ENR

1765                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN);\
1767                                             tmpreg = READ_REG(RCC->APB4ENR);\
1773                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\
1775                                             tmpreg = READ_REG(RCC->APB4ENR);\
1781                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\
1783                                             tmpreg = READ_REG(RCC->APB4ENR);\
1789                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\
1791                                             tmpreg = READ_REG(RCC->APB4ENR);\
1797                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\
1799                                             tmpreg = READ_REG(RCC->APB4ENR);\
1805                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\
1807                                             tmpreg = READ_REG(RCC->APB4ENR);\
1813                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\
1815                                             tmpreg = READ_REG(RCC->APB4ENR);\
1821                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\
1823                                             tmpreg = READ_REG(RCC->APB4ENR);\
1829                                                SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\
1831                                                tmpreg = READ_REG(RCC->APB4ENR);\
1837                                             SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\
1839                                             tmpreg = READ_REG(RCC->APB4ENR);\
1843 #define __HAL_RCC_SBS_CLK_DISABLE()     CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN)
1845 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN)
1847 #define __HAL_RCC_SPI6_CLK_DISABLE()   CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN)
1849 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN)
1851 #define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN)
1853 #define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN)
1855 #define __HAL_RCC_LPTIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN)
1857 #define __HAL_RCC_VREF_CLK_DISABLE()   CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN)
1859 #define __HAL_RCC_RTCAPB_CLK_DISABLE()    CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN)
1861 #define __HAL_RCC_DTS_CLK_DISABLE()    CLEAR_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN)
2181 #define __HAL_RCC_SBS_IS_CLK_ENABLED()     (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SBSEN) != 0U)
2183 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN) != 0U)
2185 #define __HAL_RCC_SPI6_IS_CLK_ENABLED()    (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN) != 0U)
2187 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()  (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN) != 0U)
2189 #define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()  (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN) != 0U)
2191 #define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()  (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN) != 0U)
2193 #define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()  (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN) != 0U)
2195 #define __HAL_RCC_VREF_IS_CLK_ENABLED()    (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN) != 0U)
2197 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED()     (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN) != 0U)
2199 #define __HAL_RCC_DTS_IS_CLK_ENABLED()     (READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN) != 0U)