Lines Matching refs:APB1ENR1
1343 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN);\
1345 tmpreg = READ_REG(RCC->APB1ENR1);\
1351 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN);\
1353 tmpreg = READ_REG(RCC->APB1ENR1);\
1359 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN);\
1361 tmpreg = READ_REG(RCC->APB1ENR1);\
1367 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN);\
1369 tmpreg = READ_REG(RCC->APB1ENR1);\
1375 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN);\
1377 tmpreg = READ_REG(RCC->APB1ENR1);\
1383 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN);\
1385 tmpreg = READ_REG(RCC->APB1ENR1);\
1391 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN);\
1393 tmpreg = READ_REG(RCC->APB1ENR1);\
1399 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN);\
1401 tmpreg = READ_REG(RCC->APB1ENR1);\
1407 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN);\
1409 tmpreg = READ_REG(RCC->APB1ENR1);\
1415 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN);\
1417 tmpreg = READ_REG(RCC->APB1ENR1);\
1423 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN);\
1425 tmpreg = READ_REG(RCC->APB1ENR1);\
1431 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN);\
1433 tmpreg = READ_REG(RCC->APB1ENR1);\
1439 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN);\
1441 tmpreg = READ_REG(RCC->APB1ENR1);\
1447 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN);\
1449 tmpreg = READ_REG(RCC->APB1ENR1);\
1455 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN);\
1457 tmpreg = READ_REG(RCC->APB1ENR1);\
1463 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN);\
1465 tmpreg = READ_REG(RCC->APB1ENR1);\
1471 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN);\
1473 tmpreg = READ_REG(RCC->APB1ENR1);\
1479 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN);\
1481 tmpreg = READ_REG(RCC->APB1ENR1);\
1487 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN);\
1489 tmpreg = READ_REG(RCC->APB1ENR1);\
1495 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN);\
1497 tmpreg = READ_REG(RCC->APB1ENR1);\
1503 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN);\
1505 tmpreg = READ_REG(RCC->APB1ENR1);\
1511 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN);\
1513 tmpreg = READ_REG(RCC->APB1ENR1);\
1519 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN);\
1521 tmpreg = READ_REG(RCC->APB1ENR1);\
1527 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN);\
1529 tmpreg = READ_REG(RCC->APB1ENR1);\
1535 SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN);\
1537 tmpreg = READ_REG(RCC->APB1ENR1);\
1545 tmpreg = READ_REG(RCC->APB1ENR1);\
1553 tmpreg = READ_REG(RCC->APB1ENR1);\
1561 tmpreg = READ_REG(RCC->APB1ENR1);\
1569 tmpreg = READ_REG(RCC->APB1ENR1);\
1573 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN)
1575 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN)
1577 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN)
1579 #define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN)
1581 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN)
1583 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN)
1585 #define __HAL_RCC_TIM12_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN)
1587 #define __HAL_RCC_TIM13_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN)
1589 #define __HAL_RCC_TIM14_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN)
1591 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN)
1593 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN)
1595 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN)
1597 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN)
1599 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN)
1601 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN)
1603 #define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN)
1605 #define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN)
1607 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN)
1609 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN)
1611 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN)
1613 #define __HAL_RCC_I3C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN)
1615 #define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN)
1617 #define __HAL_RCC_UART7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN)
1619 #define __HAL_RCC_UART8_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN)
2077 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U)
2079 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U)
2081 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U)
2083 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U)
2085 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U)
2087 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U)
2089 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM12EN) != 0U)
2091 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM13EN) != 0U)
2093 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM14EN) != 0U)
2095 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_LPTIM1EN) != 0U)
2097 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U)
2099 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U)
2101 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI3EN) != 0U)
2103 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPDIFRXEN) != 0U)
2105 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U)
2107 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U)
2109 #define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U)
2111 #define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U)
2113 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) != 0U)
2115 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U)
2117 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C3EN) != 0U)
2119 #define __HAL_RCC_I3C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1_I3C1EN) != 0U)
2121 #define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CECEN) != 0U)
2123 #define __HAL_RCC_UART7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART7EN) != 0U)
2125 #define __HAL_RCC_UART8_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART8EN) != 0U)