Lines Matching refs:AHB5RSTR
2368 #define __HAL_RCC_AHB5_FORCE_RESET() WRITE_REG(RCC->AHB5RSTR, 0x0018513BUL)
2369 #define __HAL_RCC_AHB5_RELEASE_RESET() WRITE_REG(RCC->AHB5RSTR, 0UL)
2371 #define __HAL_RCC_HPDMA1_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_HPDMA1RST)
2372 #define __HAL_RCC_HPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_HPDMA1RST)
2374 #define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_DMA2DRST)
2375 #define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_DMA2DRST)
2378 #define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_JPEGRST)
2379 #define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_JPEGRST)
2382 #define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_FMCRST)
2383 #define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_FMCRST)
2385 #define __HAL_RCC_XSPI1_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI1RST)
2386 #define __HAL_RCC_XSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI1RST)
2388 #define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_SDMMC1RST)
2389 #define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_SDMMC1RST)
2391 #define __HAL_RCC_XSPI2_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI2RST)
2392 #define __HAL_RCC_XSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPI2RST)
2394 #define __HAL_RCC_XSPIM_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPIMRST)
2395 #define __HAL_RCC_XSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_XSPIMRST)
2398 #define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GFXMMURST)
2399 #define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GFXMMURST)
2403 #define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GPU2DRST)
2404 #define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB5RSTR, RCC_AHB5RSTR_GPU2DRST)