Lines Matching refs:AHB5LPENR

2831 #define __HAL_RCC_HPDMA1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN)
2833 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN)
2835 #define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN)
2838 #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN)
2841 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()     SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN)
2843 #define __HAL_RCC_XSPI1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN)
2845 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN)
2847 #define __HAL_RCC_XSPI2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN)
2849 #define __HAL_RCC_XSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN)
2852 #define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()  SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN)
2856 #define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN)
2859 #define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN)
2861 #define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()   SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN)
2863 #define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()    SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN)
2865 #define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN)
2868 #define __HAL_RCC_HPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN)
2870 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN)
2872 #define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN)
2875 #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN)
2878 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()    CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN)
2880 #define __HAL_RCC_XSPI1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN)
2882 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN)
2884 #define __HAL_RCC_XSPI2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN)
2886 #define __HAL_RCC_XSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN)
2889 #define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN)
2893 #define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN)
2896 #define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN)
2898 #define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()  CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN)
2900 #define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()   CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN)
2902 #define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPEN)
3309 #define __HAL_RCC_HPDMA1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_HPDMA1LPEN…
3311 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DMA2DLPEN)…
3313 #define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FLASHLPEN)…
3316 #define __HAL_RCC_JPEG_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_JPEGLPEN) …
3319 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()     (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_FMCLPEN) !…
3321 #define __HAL_RCC_XSPI1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI1LPEN)…
3323 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_SDMMC1LPEN…
3325 #define __HAL_RCC_XSPI2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPI2LPEN)…
3327 #define __HAL_RCC_XSPIM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_XSPIMLPEN) !…
3330 #define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()  (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GFXMMULPEN…
3334 #define __HAL_RCC_GPU2D_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_GPU2DLPEN)…
3337 #define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM1LPEN)…
3339 #define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED()   (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_DTCM2LPEN)…
3341 #define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED()    (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_ITCMLPEN) …
3343 #define __HAL_RCC_AXISRAM_IS_CLK_SLEEP_ENABLED() (READ_BIT(RCC->AHB5LPENR, RCC_AHB5LPENR_AXISRAMLPE…