Lines Matching refs:AHB4ENR

1066                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\
1068                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1074                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\
1076                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1082                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\
1084                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1090                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\
1092                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1098                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\
1100                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1106                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\
1108                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1114                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\
1116                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1122                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\
1124                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1130                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN);\
1132                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1138                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN);\
1140                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1146                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN);\
1148                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1154                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN);\
1156                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1162                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\
1164                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1170                                             SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\
1172                                             tmpreg = READ_REG(RCC->AHB4ENR);\
1177 #define __HAL_RCC_GPIOA_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN)
1179 #define __HAL_RCC_GPIOB_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN)
1181 #define __HAL_RCC_GPIOC_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN)
1183 #define __HAL_RCC_GPIOD_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN)
1185 #define __HAL_RCC_GPIOE_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN)
1187 #define __HAL_RCC_GPIOF_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN)
1189 #define __HAL_RCC_GPIOG_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN)
1191 #define __HAL_RCC_GPIOH_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN)
1193 #define __HAL_RCC_GPIOM_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN)
1195 #define __HAL_RCC_GPION_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN)
1197 #define __HAL_RCC_GPIOO_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN)
1199 #define __HAL_RCC_GPIOP_CLK_DISABLE()  CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN)
1201 #define __HAL_RCC_CRC_CLK_DISABLE()    CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN)
1203 #define __HAL_RCC_BKPRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN)
1999 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN) != 0U)
2001 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN) != 0U)
2003 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN) != 0U)
2005 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN) != 0U)
2007 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN) != 0U)
2009 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN) != 0U)
2011 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN) != 0U)
2013 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN) != 0U)
2015 #define __HAL_RCC_GPIOM_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOMEN) != 0U)
2017 #define __HAL_RCC_GPION_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIONEN) != 0U)
2019 #define __HAL_RCC_GPIOO_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOOEN) != 0U)
2021 #define __HAL_RCC_GPIOP_IS_CLK_ENABLED()   (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOPEN) != 0U)
2023 #define __HAL_RCC_CRC_IS_CLK_ENABLED()     (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN) != 0U)
2025 #define __HAL_RCC_BKPRAM_IS_CLK_ENABLED()  (READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN) != 0U)