Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
61 …UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Tr…
62 …SecureFault_IRQn = -9, /*!< -9 Secure Fault …
63 …SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction …
64 …DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor …
65 …PendSV_IRQn = -2, /*!< -2 Pendable request for system service …
66 …SysTick_IRQn = -1, /*!< -1 System Tick Timer …
71 …RTC_IRQn = 2, /*!< RTC non-secure interrupt …
75 …FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt …
188 …CEC_IRQn = 119, /*!< CEC-HDMI global interrupt …
208 /* ------- Start of section using anonymous unions and disabling warnings ------- */
216 #pragma clang diagnostic ignored "-Wc11-extensions"
217 #pragma clang diagnostic ignored "-Wreserved-id-macro"
232 /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
245 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
277 * @brief Inter-integrated Circuit Interface
295 * @brief Improved Inter-integrated Circuit Interface
301 …t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
308 …t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */
311 …t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */
313 …t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */
319 …nt32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */
320 …t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */
323 …t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */
327 …t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */
343 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
344 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
345 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
346 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
347 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
348 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
349 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
350 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
351 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
405 …2_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */
419 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
422 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
423 …__IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */
431 __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */
457 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */
459 uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */
464 uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */
508 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
526 …__IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: …
527 …VED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */
531 …VED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */
539 …VED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */
540 …__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: …
737 …2_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */
738 …2_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */
740 …2_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */
743 …2_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */
754 …__IO uint32_t NSKEYR; /*!< FLASH non-secure key register, …
757 …__IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, …
761 …__IO uint32_t NSSR; /*!< FLASH non-secure status register, …
763 …__IO uint32_t NSCR; /*!< FLASH non-secure control register, …
765 …__IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, …
769 …__IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, …
775 …*!< Reserved3, Address offset: 0x58-0x5C */
776 …__IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, …
777 …__IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, …
782 …*!< Reserved4, Address offset: 0x78-0x7C */
783 …__IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, …
784 …__IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, …
789 …*!< Reserved5, Address offset: 0x98-0x9C */
790 …__IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, …
791 …__IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, …
792 …__IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, …
793 …__IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, …
794 …*!< Reserved6, Address offset: 0xB0-0xBC */
795 …__IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, …
796 …__IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, …
797 …__IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, …
798 …__IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, …
799 …*!< Reserved7, Address offset: 0xD0-0xDC */
811 …< Reserved8, Address offset: 0x10C-0x19C */
812 …__IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, …
813 …__IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, …
814 …__IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, …
815 …__IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, …
816 …< Reserved9, Address offset: 0x1B0-0x1BC */
817 …__IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, …
818 …__IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, …
819 …__IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, …
820 …__IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, …
821 …< Reserved10, Address offset: 0x1D0-0x1DC */
855 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
860 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
862 …__IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */
872 … Reserved1, Address offset: 0x04-0x0C */
880 … Reserved3, Address offset: 0x2C-0x3C */
881 …__IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, …
882 …__IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, …
883 …__IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, …
884 …__IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, …
885 …__IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, …
886 …__IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, …
887 …__IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, …
888 …__IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, …
889 …__IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, …
890 …__IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, …
891 …__IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, …
892 …__IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, …
893 …__IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, …
894 …__IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, …
895 …__IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, …
896 …__IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, …
902 … RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
904 … RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */
905 …t32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */
906 … RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */
907 …t32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
937 …uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C …
955 … uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */
978 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
984 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1032 …D1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
1035 …D2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
1041 …D5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
1047 …D8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
1053 …D11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
1055 …D12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
1057 …D13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
1063 …D16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
1065 …D17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
1071 …D20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
1073 …D21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
1083 …OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */
1084 …OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */
1085 …OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */
1086 …OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */
1087 …OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */
1088 …OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */
1089 …OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */
1090 …OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */
1091 …OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */
1097 … /*!< Reserved, Address offset: 0x004-0x00C */
1099 … /*!< Reserved, Address offset: 0x014-0x2FC */
1113 … uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
1116 … uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
1130 … uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */
1231 …uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03F…
1232 …__IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D…
1242 * @brief Real-Time Clock
1260 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x…
1298 …uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C …
1301 …uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC …
1382 …ESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */
1389 …ESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */
1391 …ESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */
1393 …ESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */
1395 …ESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */
1405 …ERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */
1406 …__IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset…
1433 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
1440 …uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C …
1476 …32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */
1531 …[4]; /*!< Reserved, 0x030 - 0x03C */
1540 …[8]; /*!< Reserved, 0x060 - 0x07C */
1549 …[8]; /*!< Reserved, 0x0A0 - 0x0BC */
1569 …[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
1571 …[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
1596 …BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1597 …__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, …
1605 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1626 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1627 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1667 … uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
1672 … uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
1677 … uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
1684 … uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0C4 */
1733 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
1735 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
1776 /* -------- End of section using anonymous unions and disabling warnings -------- */
1811 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
1812 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address …
1813 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (256 KB) non-secure base address …
1814 #define SRAM2_BASE_NS (0x20040000UL) /*!< SRAM2 (64 KB) non-secure base address …
1815 #define SRAM3_BASE_NS (0x20050000UL) /*!< SRAM3 (320 KB) non-secure base address …
1816 #define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address …
1818 /* External memories base addresses - Not aliased */
1832 /* Peripheral memory map - Non secure */
2004 /* Flash, Peripheral and internal SRAMs base addresses - Secure */
2011 /* Peripheral memory map - Secure */
2188 #define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address …
2189 #define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) …
2192 #define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */
2197 #define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */
2198 #define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */
2199 #define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */
2202 #define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base a…
2207 … (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address …
2211 … (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address …
2215 … (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address …
2220 … (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address …
2224 …S (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address …
2226 …ne FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of …
2277 * Then it jumps to the non-secure reset handler present within the
2318 * @brief RSSLib Non-secure callable function pointer structure
2741 /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
4432 … ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
4457 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
4691 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data regist…
5003 …R DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
5006 … DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
5011 …R DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
5014 …RB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data…
5019 …R DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
5022 …RB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned dat…
5027 …R DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
5030 … DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
5035 …R DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
5038 …RB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data…
5043 …R DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
5046 …RB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned dat…
5051 …R DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
5054 …R DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
5059 …R DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
5062 …R DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
5067 …R DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
5070 …R DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
6082 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap …
6114 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet spe…
6123 … ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6135 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit ma…
6159 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Pa…
6162 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Pa…
6182 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP …
6204 …wards all control frames except Pause packets to application even if they fail the Address Filter …
6207 …ARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter …
6310 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-…
6313 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
6319 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLA…
6344 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN …
6380 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN …
6416 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quan…
6526 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up …
6529 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FI…
6532 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Pa…
6538 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Pa…
6544 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Pa…
6552 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
6555 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet fi…
6613 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Vers…
6616 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined …
6670 …R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
6673 …0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
6676 …R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
6688 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Ti…
6700 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-u…
6712 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Suppo…
6756 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestam…
6979 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset…
7201 … ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
7204 … ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
7233 /* Bit definition for Ethernet MAC Sub-second Increment Register */
7236 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Incre…
7239 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond …
7249 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-second…
7262 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-secon…
7338 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timesta…
7343 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timesta…
7531 …MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes)…
7534 … ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
7578 …QDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
7582 … ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deact…
7585 … ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activ…
7651 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned B…
8002 … DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */
8005 … DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */
8008 … DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */
8011 … DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */
8014 … DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */
8017 … DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */
8020 … DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */
8023 … DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */
8054 #define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-lis…
8068 … DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag …
8094 … DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag …
8129 … DMA_CCR_ULEIE_Msk /*!< Update linked-list item error inter…
8144 #define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-lis…
8170 …k /*!< Source byte exchange within the unaligned half-word of each source w…
8193 … DMA_CTR1_DHX_Msk /*!< Destination half-word exchange …
8285 … DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */
9518 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of…
9916 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-…
9919 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-…
10080 /* HDMI-CEC (CEC) */
10137 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
10143 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
10167 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
10170 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
10178 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
10184 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
10208 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
10211 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
10222 #define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-ba…
10266 … FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area inter…
10306 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-pro…
10363 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-ope…
10424 … FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */
10477 … FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option …
10480 … FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option …
10533 … FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector at…
10551 …ATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sect…
10554 …EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */
10567 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail a…
10570 … FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */
10573 …_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */
10576 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail b…
10579 …ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */
10582 …SH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */
10596 #define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail d…
10609 … FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
10620 …UF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
10628 …F_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
10795 … FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
10802 … FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10853 … FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
10860 … FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
11183 … FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
12397 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
12402 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload…
12679 …1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
12700 …2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
12715 /*----------------------------------------------------------------------------*/
12749 …3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
12770 …4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
12785 /*----------------------------------------------------------------------------*/
12814 …5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
12830 …6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
12923 …ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
12972 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
12988 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State S…
12991 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State S…
13018 …BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
13021 …K2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
13249 … LPTIM_ISR_CC1OF_Msk /*!< Capture/Compare 1 over-capture flag */
13252 … LPTIM_ISR_CC2OF_Msk /*!< Capture/Compare 2 over-capture flag */
13293 … LPTIM_ICR_CC1OCF_Msk /*!< Capture/Compare 1 over-capture clear flag */
13296 … LPTIM_ICR_CC2OCF_Msk /*!< Capture/Compare 2 over-capture clear flag */
13337 … LPTIM_DIER_CC1OIE_Msk /*!< Capture/Compare 1 over-capture interrupt ena…
13340 … LPTIM_DIER_CC2OIE_Msk /*!< Capture/Compare 2 over-capture interrupt ena…
13826 …AIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) …
13908 …LIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable …
13911 …FAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable …
13962 … SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
14040 #define XSPI_CR_DMM XSPI_CR_DMM_Msk /*!< Dual-…
14915 …GR_REG_EN OTFDEC_REG_CONFIGR_REG_EN_Msk /*!< Region on-the-fly decryption enab…
14929 …C_REG_CONFIGR_KEYCRC OTFDEC_REG_CONFIGR_KEYCRC_Msk /*!< Region key 8-bit CRC */
14980 #define OTFDEC_ISR_XONEIF OTFDEC_ISR_XONEIF_Msk /*!< Execute-on…
14991 #define OTFDEC_ICR_XONEIF OTFDEC_ICR_XONEIF_Msk /*!< Execute-on…
15002 #define OTFDEC_IER_XONEIE OTFDEC_IER_XONEIE_Msk /*!< Execute-on…
17564 /* Real-Time Clock (RTC) */
17801 …_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
19508 #define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-…
19530 #define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode…
19533 #define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode…
19536 #define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode…
19539 #define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode…
19549 …e SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */
19551 …_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation In…
19552 … (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt e…
19553 …_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt …
19554 …_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt e…
19555 …_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Inter…
19556 …_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt en…
19645 #define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Sec…
20956 … UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC de…
20959 …XFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC de…
21007 …R_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
21035 … UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
21044 … UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to…
21047 … UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to…
21094 #define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role …
21123 … UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected inter…
21154 #define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role …
21195 #define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role …
21224 …LID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
21234 #define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit rece…
21316 …T_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
21325 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
21350 …T_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
21370 …DDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detec…
21414 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-…
21417 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
21422 …_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
21436 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-P…
21439 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duple…
21478 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
21535 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud …
21592 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud …
21595 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud …
21750 /* Inter-integrated Circuit Interface (I2C) */
21819 #define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Pl…
21836 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit add…
21839 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit add…
21868 …A1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
22030 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit rece…
22035 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit tran…
22040 /* Improved Inter-integrated Circuit Interface (I3C) */
22052 #define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC …
22085 #define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keepe…
22240 …ER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */
22251 … /*!< Target Address Received during accepted IBI or Controller-role request */
22295 … I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */
22298 …DF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */
22366 … I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable…
22369 … I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt…
22425 …RF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */
22428 …F I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Fla…
22478 …R0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */
22505 … I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from…
22535 … I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */
22538 …GR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
22541 …C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C …
22618 …HOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */
22639 #define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-d…
22733 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
22739 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC …
22811 …IDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
22899 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet a…
22902 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet s…
22917 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet a…
23085 … WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to L…
23100 … WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
23190 … USB_ISTR_IDN_Msk /*!< EndPoint IDentifier (read-only bit) Mask */
23193 … USB_ISTR_DIR_Msk /*!< DIRection of transaction (read-only bit) Mask */
23199 … USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame (clear-only bit) Mask */
23202 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame (clear-…
23208 #define USB_ISTR_DCON USB_ISTR_DCON_Msk /*!< HOST MODE-Device Conne…
23211 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< SUSPend (clear-only bi…
23214 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< WaKe UP (clear-only bi…
23217 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< ERRor (clear-only bit)…
23220 …OVR USB_ISTR_PMAOVR_Msk /*!< PMA OVeR/underrun (clear-only bit) Mask */
23223 …R USB_ISTR_CTR_Msk /*!< Correct TRansfer (clear-only bit) Mask */
23246 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< status of D- data line…
23326 #define USB_BCDR_DPPU USB_BCDR_DPPU_Msk /*!< DP Pull-up Enable Mask…
23329 #define USB_BCDR_DPPD USB_BCDR_DPPD_Msk /*!< DP Pull-Down Enable Ma…
23553 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23554 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23557 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23560 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23561 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23562 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23563 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23564 #define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23565 #define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23566 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23567 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23568 #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23569 #define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23572 #define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23573 #define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23574 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23575 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23578 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23579 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23580 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23581 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23582 #define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23583 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23584 #define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23585 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23586 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23587 #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23590 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23591 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23592 #define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23595 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23596 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23597 #define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23598 #define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23599 #define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23600 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23601 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23602 #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23605 #define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23608 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23609 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23610 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23611 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23612 #define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23613 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23614 #define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23615 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23616 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23617 #define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23618 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23619 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23622 #define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23623 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23624 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23625 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
23626 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
23630 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23631 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23632 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23633 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23634 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23635 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23636 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23637 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23638 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23639 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23640 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23641 #define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23642 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23645 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23648 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23649 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23650 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23651 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23652 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23653 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23654 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23657 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23660 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23661 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23662 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23663 #define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23666 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23669 #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23670 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23671 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23674 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23677 #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23678 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23679 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23682 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23685 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23686 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23687 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23690 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23693 #define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23694 #define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23695 #define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23698 #define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23701 #define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23702 #define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23703 #define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23704 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23707 #define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23710 #define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23711 #define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23712 #define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23715 #define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23718 #define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23719 #define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23720 #define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23721 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23724 #define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23727 #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23728 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23729 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23730 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23733 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
23736 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23737 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23738 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
23739 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23742 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23745 #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23746 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23747 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23748 #define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23749 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23750 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23751 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23752 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23753 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23754 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23757 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23758 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23759 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23762 #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23763 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23764 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23765 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23766 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23767 #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23768 #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23769 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23770 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23771 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23772 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23773 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23774 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23777 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23778 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23779 #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23782 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23783 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23784 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23785 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23786 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23787 #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
23790 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23791 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
23792 #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
24274 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
24492 /******************** UART Instances : Half-Duplex mode **********************/
24536 /******************** UART Instances : Wake-up from Stop mode **********************/