Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
61 …UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Tr…
62 …SecureFault_IRQn = -9, /*!< -9 Secure Fault …
63 …SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction …
64 …DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor …
65 …PendSV_IRQn = -2, /*!< -2 Pendable request for system service …
66 …SysTick_IRQn = -1, /*!< -1 System Tick Timer …
71 …RTC_IRQn = 2, /*!< RTC non-secure interrupt …
75 …FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt …
180 …CEC_IRQn = 119, /*!< CEC-HDMI global interrupt …
200 /* ------- Start of section using anonymous unions and disabling warnings ------- */
208 #pragma clang diagnostic ignored "-Wc11-extensions"
209 #pragma clang diagnostic ignored "-Wreserved-id-macro"
224 /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
237 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
269 * @brief Inter-integrated Circuit Interface
287 * @brief Improved Inter-integrated Circuit Interface
293 …t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
300 …t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */
303 …t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */
305 …t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */
311 …nt32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */
312 …t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */
315 …t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */
319 …t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */
335 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
336 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
337 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
338 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
339 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
340 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
341 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
342 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
343 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
377 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
380 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
381 …__IO uint32_t CSR[103]; /*!< HASH context swap registers, Address offset: 0x0F8-0x290 */
389 __IO uint32_t HR[16]; /*!< HASH digest registers, Address offset: 0x310-0x34C */
415 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */
417 uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */
422 uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */
466 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
484 …__IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: …
485 …VED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */
489 …VED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */
497 …VED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */
498 …__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: …
522 …2_t RESERVED2[9]; /*!< Reserved 2, 0x3C-- 0x5C */
523 …2_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */
525 …2_t RESERVED3[3]; /*!< Reserved 3, 0x74 -- 0x7C */
528 …2_t RESERVED4[2]; /*!< Reserved 4, 0x88 -- 0x8C */
539 …__IO uint32_t NSKEYR; /*!< FLASH non-secure key register, …
542 …__IO uint32_t NSOBKKEYR; /*!< FLASH non-secure option bytes keys key register, …
546 …__IO uint32_t NSSR; /*!< FLASH non-secure status register, …
548 …__IO uint32_t NSCR; /*!< FLASH non-secure control register, …
550 …__IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, …
554 …__IO uint32_t NSOBKCFGR; /*!< FLASH non-secure option byte key configuration register, …
560 …*!< Reserved3, Address offset: 0x58-0x5C */
561 …__IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, …
562 …__IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, …
567 …*!< Reserved4, Address offset: 0x78-0x7C */
568 …__IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, …
569 …__IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, …
574 …*!< Reserved5, Address offset: 0x98-0x9C */
575 …__IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, …
576 …__IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, …
577 …__IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, …
578 …__IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, …
579 …*!< Reserved6, Address offset: 0xB0-0xBC */
580 …__IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, …
581 …__IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, …
582 …__IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, …
583 …__IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, …
584 …*!< Reserved7, Address offset: 0xD0-0xDC */
596 …< Reserved8, Address offset: 0x10C-0x19C */
597 …__IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, …
598 …__IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, …
599 …__IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, …
600 …__IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, …
601 …< Reserved9, Address offset: 0x1B0-0x1BC */
602 …__IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, …
603 …__IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, …
604 …__IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, …
605 …__IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, …
606 …< Reserved10, Address offset: 0x1D0-0x1DC */
640 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
645 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
647 …__IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */
657 … Reserved1, Address offset: 0x04-0x0C */
665 … Reserved3, Address offset: 0x2C-0x3C */
666 …__IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, …
667 …__IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, …
668 …__IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, …
669 …__IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, …
670 …__IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, …
671 …__IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, …
672 …__IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, …
673 …__IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, …
674 …__IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, …
675 …__IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, …
676 …__IO uint32_t MPCWM3BCFGR; /*!< TZSC memory 3 sub-region B watermark configuration register, …
677 …__IO uint32_t MPCWM3BR; /*!< TZSC memory 3 sub-region B watermark register, …
678 …__IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, …
679 …__IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, …
680 …__IO uint32_t MPCWM4BCFGR; /*!< TZSC memory 4 sub-region B watermark configuration register, …
681 …__IO uint32_t MPCWM4BR; /*!< TZSC memory 4 sub-region B watermark register, …
687 … RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */
689 … RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */
690 …t32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x17C */
691 … RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x1FC */
692 …t32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
722 …uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C …
740 … uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */
763 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
769 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
817 …D1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
820 …D2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
826 …D5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
832 …D8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
838 …D11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
840 …D12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
842 …D13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
848 …D16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
850 …D17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
856 …D20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
858 …D21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
871 … uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
874 … uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
888 … uint32_t RESERVED4[43];/*!< Reserved, Address offset: 0x54-0xFC */
989 …uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03F…
990 …__IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D…
1000 * @brief Real-Time Clock
1018 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x…
1056 …uint32_t RESERVED1[3];/*!< Reserved, Address offset: 0x44 -- 0x4C …
1059 …uint32_t RESERVED2[42];/*!< Reserved, Address offset: 0x58 -- 0xFC …
1140 …ESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */
1147 …ESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */
1149 …ESERVED4[26]; /*!< RESERVED4, Address offset: 0x38 - 0x9C */
1151 …ESERVED5[7]; /*!< RESERVED5, Address offset: 0xA4 - 0xBC */
1153 …ESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */
1163 …ERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */
1164 …__IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset…
1191 …uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C …
1198 …uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C …
1234 …32_t RESERVED[949];/*!< Reserved, Address offset: 0x3C -- 0x3F0 */
1289 …[4]; /*!< Reserved, 0x030 - 0x03C */
1298 …[8]; /*!< Reserved, 0x060 - 0x07C */
1307 …[8]; /*!< Reserved, 0x0A0 - 0x0BC */
1327 …[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
1329 …[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
1354 …BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR)…
1355 …__IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, …
1363 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1384 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1385 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1425 … uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
1430 … uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
1435 … uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
1442 … uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0C4 */
1491 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
1493 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
1534 /* -------- End of section using anonymous unions and disabling warnings -------- */
1569 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
1570 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address …
1571 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (256 KB) non-secure base address …
1572 #define SRAM2_BASE_NS (0x20040000UL) /*!< SRAM2 (64 KB) non-secure base address …
1573 #define SRAM3_BASE_NS (0x20050000UL) /*!< SRAM3 (320 KB) non-secure base address …
1574 #define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address …
1576 /* External memories base addresses - Not aliased */
1590 /* Peripheral memory map - Non secure */
1750 /* Flash, Peripheral and internal SRAMs base addresses - Secure */
1757 /* Peripheral memory map - Secure */
1922 #define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address …
1923 #define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) …
1926 #define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */
1931 #define FLASH_EDATA_BASE_NS (0x09000000UL) /*!< FLASH high-cycle data non-secure base address */
1932 #define FLASH_EDATA_BASE_S (0x0D000000UL) /*!< FLASH high-cycle data secure base address */
1933 #define FLASH_EDATA_SIZE (0x18000U) /*!< 96 KB of Flash high-cycle data */
1936 #define FLASH_OBK_BASE_NS (0x0BFD0000UL) /*!< FLASH OBK (option byte keys) non-secure base a…
1941 … (FLASH_OBK_BASE_NS + FLASH_OBK_HDPL0_SIZE) /*!< FLASH OBK HDPL1 non-secure base address …
1945 … (FLASH_OBK_HDPL1_BASE_NS + FLASH_OBK_HDPL1_SIZE) /*!< FLASH OBK HDPL2 non-secure base address …
1949 … (FLASH_OBK_HDPL2_BASE_NS + FLASH_OBK_HDPL2_SIZE) /*!< FLASH OBK HDPL3 non-secure base address …
1954 … (FLASH_OBK_HDPL3_BASE_NS) /*!< FLASH OBK HDPL3 non-secure base address …
1958 …S (FLASH_OBK_HDPL3_BASE_NS + FLASH_OBK_HDPL3S_SIZE) /*!< FLASH OBK HDPL3 non-secure base address …
1960 …ne FLASH_OBK_HDPL3NS_SIZE (FLASH_OBK_HDPL3_SIZE - FLASH_OBK_HDPL3S_SIZE) /*!< 2032 Bytes of …
2011 * Then it jumps to the non-secure reset handler present within the
2052 * @brief RSSLib Non-secure callable function pointer structure
2427 /*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */
4053 … ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
4078 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
4312 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data regist…
4624 …R DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
4627 … DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
4632 …R DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
4635 …RB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data…
4640 …R DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
4643 …RB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned dat…
4648 …R DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
4651 … DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
4656 …R DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
4659 …RB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data…
4664 …R DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
4667 …RB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned dat…
4672 …R DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
4675 …R DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
4680 …R DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
4683 …R DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
4688 …R DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
4691 …R DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
5509 … DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */
5512 … DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */
5515 … DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */
5518 … DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */
5521 … DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */
5524 … DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */
5527 … DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */
5530 … DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */
5561 #define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-lis…
5575 … DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag …
5601 … DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag …
5636 … DMA_CCR_ULEIE_Msk /*!< Update linked-list item error inter…
5651 #define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-lis…
5677 …k /*!< Source byte exchange within the unaligned half-word of each source w…
5700 … DMA_CTR1_DHX_Msk /*!< Destination half-word exchange …
5792 … DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */
7025 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of…
7423 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-…
7426 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-…
7587 /* HDMI-CEC (CEC) */
7644 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Rec…
7650 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun …
7674 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer U…
7677 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error …
7685 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Rec…
7691 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun …
7715 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer U…
7718 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT…
7729 #define FLASH_BLOCKBASED_NB_REG (4U) /*!< 4 Block-ba…
7773 … FLASH_OPSR_DATA_OP_Msk /*!< Operation in Flash high-cycle data area inter…
7813 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-pro…
7870 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-ope…
7931 … FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */
7984 … FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option …
7987 … FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option …
8040 … FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector at…
8058 …ATA_STRT FLASH_EDATAR_EDATA_STRT_Msk /*!< Flash high-cycle data start sect…
8061 …EDATA_EN FLASH_EDATAR_EDATA_EN_Msk /*!< Flash high-cycle data enable */
8074 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail a…
8077 … FLASH_ECCR_OBK_ECC_Msk /*!< Flash OB Keys storage area ECC fail */
8080 …_ECC FLASH_ECCR_DATA_ECC_Msk /*!< Flash high-cycle data ECC fail */
8083 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail b…
8086 …ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */
8089 …SH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */
8103 #define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail d…
8116 … FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */
8127 …UF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */
8135 …F_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */
8302 … FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
8309 … FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8360 … FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) …
8367 … FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8690 … FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
9904 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
9909 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload…
10186 …1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
10207 …2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
10222 /*----------------------------------------------------------------------------*/
10256 …3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
10277 …4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
10292 /*----------------------------------------------------------------------------*/
10321 …5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
10337 …6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
10430 …ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
10479 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
10495 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State S…
10498 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State S…
10525 …BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
10528 …K2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
10756 … LPTIM_ISR_CC1OF_Msk /*!< Capture/Compare 1 over-capture flag */
10759 … LPTIM_ISR_CC2OF_Msk /*!< Capture/Compare 2 over-capture flag */
10800 … LPTIM_ICR_CC1OCF_Msk /*!< Capture/Compare 1 over-capture clear flag */
10803 … LPTIM_ICR_CC2OCF_Msk /*!< Capture/Compare 2 over-capture clear flag */
10844 … LPTIM_DIER_CC1OIE_Msk /*!< Capture/Compare 1 over-capture interrupt ena…
10847 … LPTIM_DIER_CC2OIE_Msk /*!< Capture/Compare 2 over-capture interrupt ena…
11333 …AIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) …
11415 …LIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable …
11418 …FAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable …
11469 … SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
11547 #define XSPI_CR_DMM XSPI_CR_DMM_Msk /*!< Dual-…
14919 /* Real-Time Clock (RTC) */
15156 …_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
16863 #define SBS_DBGCR_DBG_AUTH_SEC SBS_DBGCR_DBG_AUTH_SEC_Msk /*!< Open the non-…
16885 #define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode…
16888 #define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode…
16891 #define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode…
16894 #define SBS_PMCR_PB9_FMP SBS_PMCR_PB9_FMP_Msk /*!< Fast-mode…
16904 …e SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */
16906 …_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation In…
16907 … (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt e…
16908 …_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt …
16909 …_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt e…
16910 …_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Inter…
16911 …_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt en…
17000 #define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Sec…
18231 … UCPD_CFG2_RXFILTDIS_Msk /*!< Enables an Rx pre-filter for the BMC de…
18234 …XFILT2N3_Msk /*!< Controls the sampling method for an Rx pre-filter for the BMC de…
18282 …R_ANASUBMODE UCPD_CR_ANASUBMODE_Msk /*!< Analog PHY sub-mode */
18310 … UCPD_CR_FRSTX_Msk /*!< Signal Fast Role Swap request */
18319 … UCPD_CR_CC1TCDIS_Msk /*!< The bit allows the Type-C detector for CC0 to…
18322 … UCPD_CR_CC2TCDIS_Msk /*!< The bit allows the Type-C detector for CC2 to…
18369 #define UCPD_IMR_FRSEVTIE UCPD_IMR_FRSEVTIE_Msk /*!< Fast Role …
18398 … UCPD_SR_RXORDDET_Msk /*!< Rx ordered set (4 K-codes) detected inter…
18429 #define UCPD_SR_FRSEVT UCPD_SR_FRSEVT_Msk /*!< Fast Role …
18470 #define UCPD_ICR_FRSEVTCF UCPD_ICR_FRSEVTCF_Msk /*!< Fast Role …
18499 …LID UCPD_RX_ORDSET_RXSOPKINVALID_Msk /*!< Rx Ordered Set corrupted K-Codes (Debug) */
18509 #define UCPD_RXDR_RXDATA UCPD_RXDR_RXDATA_Msk /*!< 8-bit rece…
18591 …T_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
18600 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
18625 …T_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
18645 …DDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detec…
18689 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-…
18692 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
18697 …_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
18711 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-P…
18714 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duple…
18753 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
18810 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud …
18867 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud …
18870 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud …
19025 /* Inter-integrated Circuit Interface (I2C) */
19094 #define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Pl…
19111 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit add…
19114 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit add…
19143 …A1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
19305 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit rece…
19310 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit tran…
19315 /* Improved Inter-integrated Circuit Interface (I3C) */
19327 #define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC …
19360 #define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keepe…
19515 …ER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */
19526 … /*!< Target Address Received during accepted IBI or Controller-role request */
19570 … I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */
19573 …DF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */
19641 … I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable…
19644 … I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt…
19700 …RF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */
19703 …F I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Fla…
19753 …R0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */
19780 … I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from…
19810 … I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */
19813 …GR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
19816 …C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C …
19893 …HOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */
19914 #define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-d…
20008 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
20014 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC …
20086 …IDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
20174 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet a…
20177 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet s…
20192 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet a…
20360 … WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to L…
20375 … WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
20465 … USB_ISTR_IDN_Msk /*!< EndPoint IDentifier (read-only bit) Mask */
20468 … USB_ISTR_DIR_Msk /*!< DIRection of transaction (read-only bit) Mask */
20474 … USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame (clear-only bit) Mask */
20477 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame (clear-…
20483 #define USB_ISTR_DCON USB_ISTR_DCON_Msk /*!< HOST MODE-Device Conne…
20486 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< SUSPend (clear-only bi…
20489 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< WaKe UP (clear-only bi…
20492 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< ERRor (clear-only bit)…
20495 …OVR USB_ISTR_PMAOVR_Msk /*!< PMA OVeR/underrun (clear-only bit) Mask */
20498 …R USB_ISTR_CTR_Msk /*!< Correct TRansfer (clear-only bit) Mask */
20521 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< status of D- data line…
20601 #define USB_BCDR_DPPU USB_BCDR_DPPU_Msk /*!< DP Pull-up Enable Mask…
20604 #define USB_BCDR_DPPD USB_BCDR_DPPD_Msk /*!< DP Pull-Down Enable Ma…
20828 #define PKA_MONTGOMERY_PARAM_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20829 #define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20832 #define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20835 #define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20836 #define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20837 #define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20838 #define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20839 #define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20840 #define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20841 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20842 #define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20843 #define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20844 #define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20847 #define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20848 #define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20849 #define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20850 #define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20853 #define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20854 #define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20855 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20856 #define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20857 #define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20858 #define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20859 #define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20860 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20861 #define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20862 #define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20865 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20866 #define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20867 #define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20870 #define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20871 #define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20872 #define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20873 #define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20874 #define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20875 #define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20876 #define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20877 #define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20880 #define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20883 #define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20884 #define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20885 #define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20886 #define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20887 #define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20888 #define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20889 #define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20890 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20891 #define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20892 #define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20893 #define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20894 #define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20897 #define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20898 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20899 #define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20900 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
20901 #define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Ext…
20905 #define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20906 #define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20907 #define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20908 #define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20909 #define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20910 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20911 #define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20912 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20913 #define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20914 #define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20915 #define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20916 #define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20917 #define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20920 #define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20923 #define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20924 #define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20925 #define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20926 #define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20927 #define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20928 #define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20929 #define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20932 #define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20935 #define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20936 #define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20937 #define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20938 #define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20941 #define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
20944 #define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20945 #define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20946 #define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20949 #define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20952 #define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20953 #define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20954 #define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20957 #define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20960 #define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20961 #define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20962 #define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20965 #define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20968 #define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20969 #define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20970 #define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20973 #define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20976 #define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20977 #define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20978 #define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20979 #define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
20982 #define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20985 #define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20986 #define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20987 #define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
20990 #define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
20993 #define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20994 #define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20995 #define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
20996 #define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
20999 #define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
21002 #define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
21003 #define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
21004 #define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
21005 #define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21008 #define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Out…
21011 #define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
21012 #define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
21013 #define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Inp…
21014 #define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21017 #define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21020 #define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21021 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21022 #define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21023 #define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21024 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21025 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21026 #define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21027 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21028 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21029 #define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21032 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21033 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21034 #define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21037 #define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21038 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21039 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21040 #define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21041 #define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21042 #define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21043 #define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21044 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21045 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21046 #define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21047 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21048 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21049 #define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21052 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21053 #define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21054 #define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21057 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21058 #define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21059 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21060 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21061 #define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21062 #define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Inpu…
21065 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21066 #define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21067 #define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Outp…
21539 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
21757 /******************** UART Instances : Half-Duplex mode **********************/
21801 /******************** UART Instances : Wake-up from Stop mode **********************/