Lines Matching +full:fail +full:- +full:fast
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
20 * If no LICENSE file comes with this software, it is provided AS-IS.
53 /* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ============…
54 …Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset …
55 …NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempte…
56 …HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault …
57 …MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Vio…
59 …BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other add…
61 …UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Tr…
62 …SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction …
63 …DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor …
64 …PendSV_IRQn = -2, /*!< -2 Pendable request for system service …
65 …SysTick_IRQn = -1, /*!< -1 System Tick Timer …
70 …RTC_IRQn = 2, /*!< RTC non-secure interrupt …
73 …FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt …
153 /* ------- Start of section using anonymous unions and disabling warnings ------- */
161 #pragma clang diagnostic ignored "-Wc11-extensions"
162 #pragma clang diagnostic ignored "-Wreserved-id-macro"
176 /* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */
189 #include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */
221 * @brief Inter-integrated Circuit Interface
239 * @brief Improved Inter-integrated Circuit Interface
245 …t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
252 …t RESERVED2[2]; /*!< Reserved, Address offset: 0x28-0x2C */
255 …t RESERVED3[2]; /*!< Reserved, Address offset: 0x38-0x3C */
257 …t RESERVED4[3]; /*!< Reserved, Address offset: 0x44-0x4C */
263 …nt32_t DEVRX[4]; /*!< I3C Target x (1<=x<=4) register, Address offset: 0x64-0x70 */
264 …t RESERVED6[7]; /*!< Reserved, Address offset: 0x74-0x8C */
267 …t RESERVED7[2]; /*!< Reserved, Address offset: 0x98-0x9C */
271 …t RESERVED9[5]; /*!< Reserved, Address offset: 0xAC-0xBC */
287 …__IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offs…
288 …__IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offs…
289 …__IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offs…
290 …__IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offs…
291 …__IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offs…
292 …__IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offs…
293 …__IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offs…
294 …__IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offs…
295 …__IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offs…
329 …__IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
332 … uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
333 …__IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
341 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
366 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 - 0x1C */
368 uint32_t RESERVED2[54]; /*!< Reserved, 0x24 - 0xF8 */
373 uint32_t RESERVED3[945]; /*!< Reserved, 0x10C - 0xFCC */
403 …__IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: …
404 …VED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */
408 …VED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */
416 …VED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */
417 …__IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: …
441 …2_t RESERVED4[9]; /*!< Reserved 4, 0x3C-- 0x5C */
442 …2_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */
443 …2_t RESERVED5[4]; /*!< Reserved 5, 0x70 -- 0x7C */
446 …2_t RESERVED6[2]; /*!< Reserved 6, 0x88 -- 0x8C */
457 …__IO uint32_t NSKEYR; /*!< FLASH non-secure key register, …
460 …*!< Reserved2, Address offset: 0x10-0x14 */
463 …__IO uint32_t NSSR; /*!< FLASH non-secure status register, …
465 …__IO uint32_t NSCR; /*!< FLASH non-secure control register, …
467 …__IO uint32_t NSCCR; /*!< FLASH non-secure clear control register, …
468 …*!< Reserved5, Address offset: 0x34-0x38 */
470 …*!< Reserved6, Address offset: 0x40-0x44 */
475 …*!< Reserved8, Address offset: 0x58-0x5C */
476 …__IO uint32_t NSEPOCHR_CUR; /*!< FLASH non-secure epoch current register, …
477 …__IO uint32_t NSEPOCHR_PRG; /*!< FLASH non-secure epoch to program register, …
478 …*!< Reserved9, Address offset: 0x68-0x6C */
481 …*!< Reserved10, Address offset: 0x78-0x7C */
482 …__IO uint32_t NSBOOTR_CUR; /*!< FLASH non-secure unique boot entry current register, …
483 …__IO uint32_t NSBOOTR_PRG; /*!< FLASH non-secure unique boot entry to program register, …
484 …*!< Reserved11, Address offset: 0x88-0x8C */
487 …*!< Reserved12, Address offset: 0x98-0xBC */
488 …__IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, …
489 …*!< Reserved13, Address offset: 0xC4-0xE4 */
492 …*!< Reserved14, Address offset: 0xF0-0xF4 */
498 …< Reserved15, Address offset: 0x10C-0x1BC */
499 …__IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, …
500 …< Reserved16, Address offset: 0x1C4-0x1E4 */
503 …< Reserved17, Address offset: 0x1F0-0x1F4 */
516 …__IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
521 …__IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
523 …__IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */
532 … Reserved1, Address offset: 0x00-0x1C */
536 … Reserved3, Address offset: 0x2C-0x6C */
537 …__IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, …
538 …__IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, …
543 … RESERVED1[128]; /*!< Reserved1, Address offset: 0x000-0x1FC */
544 …t32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */
576 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
582 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
661 … uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x08-0x0C */
664 … uint32_t RESERVED2[2]; /*!< Reserved, Address offset: 0x18-0x1C */
678 … uint32_t RESERVED6[43];/*!< Reserved, Address offset: 0x54-0xFC */
778 * @brief Real-Time Clock
796 …__IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x…
834 …uint32_t RESERVED2[3];/*!< Reserved, Address offset: 0x44 -- 0x4C …
837 …uint32_t RESERVED3[42];/*!< Reserved, Address offset: 0x58 -- 0xFC …
896 …ESERVED1[4]; /*!< RESERVED1, Address offset: 0x00 - 0x0C */
899 …ESERVED2[2]; /*!< RESERVED2, Address offset: 0x18 - 0x1C */
902 …ESERVED3[3]; /*!< RESERVED3, Address offset: 0x28 - 0x30 */
903 …ESERVED4[36]; /*!< RESERVED4, Address offset: 0x34 - 0xC0 */
904 …ESERVED6[15]; /*!< RESERVED6, Address offset: 0xC4 - 0xFC */
914 …ERVED9[8]; /*!< RESERVED9, Address offset: 0x124 - 0x140 */
915 …__IO uint32_t CNSLCKR; /*!< SBS CPU Non-secure Lock Register, Address offset…
970 …[4]; /*!< Reserved, 0x030 - 0x03C */
979 …[8]; /*!< Reserved, 0x060 - 0x07C */
988 …[8]; /*!< Reserved, 0x0A0 - 0x0BC */
1008 …[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */
1010 …[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */
1043 … uint32_t RESERVED5[4]; /*!< Reserved, 0x50 - 0x5C */
1048 … uint32_t RESERVED6[4]; /*!< Reserved, 0x70 - 0x7C */
1053 … uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
1060 … uint32_t RESERVED10[4];/*!< Reserved, 0x0B8 - 0x0C4 */
1098 …uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C …
1100 …uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C …
1141 /* -------- End of section using anonymous unions and disabling warnings -------- */
1176 /* Flash, Peripheral and internal SRAMs base addresses - Non secure */
1177 #define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 128 KB) non-secure base address …
1178 #define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (16 KB) non-secure base address …
1179 #define SRAM2_BASE_NS (0x20004000UL) /*!< SRAM2 (16 KB) non-secure base address …
1180 #define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address …
1182 /* Peripheral memory map - Non secure */
1287 #define FLASH_OTP_BASE (0x08FFF000UL) /*!< FLASH OTP (one-time programmable) base address …
1288 #define FLASH_OTP_SIZE (0x800U) /*!< 2048 bytes OTP (one-time programmable) …
1291 #define FLASH_SYSTEM_BASE_NS (0x0BF80000UL) /*!< FLASH System non-secure base address */
2488 … ADC_DIFSEL_DIFSEL_Msk /*!< ADC channel differential or single-ended mode */
2513 … ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factor in single-ended mode */
2852 … CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data regist…
3144 …R DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
3147 … DAC_DHR12R1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Right-aligned data B */
3152 …R DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
3155 …RB DAC_DHR12L1_DACC1DHRB_Msk /*!<DAC channel1 12-bit Left aligned data…
3160 …R DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
3163 …RB DAC_DHR8R1_DACC1DHRB_Msk /*!<DAC channel1 8-bit Right aligned dat…
3168 …R DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
3171 … DAC_DHR12R2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Right-aligned data B */
3176 …R DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
3179 …RB DAC_DHR12L2_DACC2DHRB_Msk /*!<DAC channel2 12-bit Left aligned data…
3184 …R DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
3187 …RB DAC_DHR8R2_DACC2DHRB_Msk /*!<DAC channel2 8-bit Right aligned dat…
3192 …R DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned dat…
3195 …R DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned dat…
3200 …R DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data…
3203 …R DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data…
3208 …R DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned dat…
3211 …R DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned dat…
3735 … DMA_MISR_MIS0_Msk /*!< Masked Interrupt State of Non-Secure Channel 0 */
3738 … DMA_MISR_MIS1_Msk /*!< Masked Interrupt State of Non-Secure Channel 1 */
3741 … DMA_MISR_MIS2_Msk /*!< Masked Interrupt State of Non-Secure Channel 2 */
3744 … DMA_MISR_MIS3_Msk /*!< Masked Interrupt State of Non-Secure Channel 3 */
3747 … DMA_MISR_MIS4_Msk /*!< Masked Interrupt State of Non-Secure Channel 4 */
3750 … DMA_MISR_MIS5_Msk /*!< Masked Interrupt State of Non-Secure Channel 5 */
3753 … DMA_MISR_MIS6_Msk /*!< Masked Interrupt State of Non-Secure Channel 6 */
3756 … DMA_MISR_MIS7_Msk /*!< Masked Interrupt State of Non-Secure Channel 7 */
3762 #define DMA_CLBAR_LBA DMA_CLBAR_LBA_Msk /*!< Linked-lis…
3776 … DMA_CFCR_ULEF_Msk /*!< Update linked-list item error flag …
3802 … DMA_CSR_ULEF_Msk /*!< Update linked-list item error flag …
3837 … DMA_CCR_ULEIE_Msk /*!< Update linked-list item error inter…
3852 #define DMA_CCR_LAP DMA_CCR_LAP_Msk /*!< Linked-lis…
3878 …k /*!< Source byte exchange within the unaligned half-word of each source w…
3898 … DMA_CTR1_DHX_Msk /*!< Destination half-word exchange …
3987 … DMA_CLLR_LA_Msk /*!< Pointer to the next linked-list data structure */
4833 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of…
5231 #define FDCAN_RXGFC_ANFE FDCAN_RXGFC_ANFE_Msk /*!<Accept Non-…
5234 #define FDCAN_RXGFC_ANFS FDCAN_RXGFC_ANFS_Msk /*!<Accept Non-…
5398 #define FLASH_BLOCKBASED_NB_REG (1U) /*!< 1 Block-ba…
5479 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-pro…
5530 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-ope…
5576 … FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */
5613 … FLASH_OPTSR_IO_VDD_HSLV_Msk /*!< VDD I/O high-speed at low-voltage option …
5616 … FLASH_OPTSR_IO_VDDIO2_HSLV_Msk /*!< VDDIO2 I/O high-speed at low-voltage option …
5660 … FLASH_PRIVBBR_PRIVBB_Msk /*!< Privileged/unprivileged 8-Kbyte Flash sector at…
5680 #define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail a…
5683 #define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail b…
5686 …ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */
5689 …SH_ECCR_OTP_ECC FLASH_ECCR_OTP_ECC_Msk /*!< Flash OTP ECC fail */
5703 #define FLASH_ECCDR_FAIL_DATA FLASH_ECCDR_FAIL_DATA_Msk /*!< ECC fail d…
6739 … TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selectio…
6744 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload…
7021 …1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
7042 …2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
7057 /*----------------------------------------------------------------------------*/
7091 …3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
7112 …4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
7127 /*----------------------------------------------------------------------------*/
7156 …5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
7172 …6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 6 Fast enable */
7265 …ARR TIM_ARR_ARR_Msk /*!<Actual auto-reload Value */
7314 … TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
7330 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State S…
7333 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State S…
7360 …BKDSRM TIM_BDTR_BKDSRM_Msk /*!<Break disarming/re-arming */
7363 …K2DSRM TIM_BDTR_BK2DSRM_Msk /*!<Break2 disarming/re-arming */
7591 … LPTIM_ISR_CC1OF_Msk /*!< Capture/Compare 1 over-capture flag */
7594 … LPTIM_ISR_CC2OF_Msk /*!< Capture/Compare 2 over-capture flag */
7635 … LPTIM_ICR_CC1OCF_Msk /*!< Capture/Compare 1 over-capture clear flag */
7638 … LPTIM_ICR_CC2OCF_Msk /*!< Capture/Compare 2 over-capture clear flag */
7679 … LPTIM_DIER_CC1OIE_Msk /*!< Capture/Compare 1 over-capture interrupt ena…
7682 … LPTIM_DIER_CC2OIE_Msk /*!< Capture/Compare 2 over-capture interrupt ena…
9410 /* Real-Time Clock (RTC) */
9647 …_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
10701 #define SBS_PMCR_PB6_FMP SBS_PMCR_PB6_FMP_Msk /*!< Fast-mode…
10704 #define SBS_PMCR_PB7_FMP SBS_PMCR_PB7_FMP_Msk /*!< Fast-mode…
10707 #define SBS_PMCR_PB8_FMP SBS_PMCR_PB8_FMP_Msk /*!< Fast-mode…
10711 …e SBS_FPUIMR_FPU_IE_Msk (0x3FUL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x0000003F - */
10713 …_0 (0x1UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000001 - Invalid operation In…
10714 … (0x2UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000002 - Divide-by-zero Interrupt e…
10715 …_2 (0x4UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000004 - Underflow Interrupt …
10716 …_3 (0x8UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000008 - Overflow Interrupt e…
10717 …_4 (0x10UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000010 - Input denormal Inter…
10718 …_5 (0x20UL << SBS_FPUIMR_FPU_IE_Pos) /*!< 0x00000020 - Inexact Interrupt en…
10796 #define SBS_CNSLCKR_LOCKNSMPU SBS_CNSLCKR_LOCKNSMPU_Msk /*!< Disable Non-Sec…
11061 …T_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
11070 … USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
11095 …T_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
11115 …DDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detec…
11159 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-…
11162 … USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
11167 …_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
11181 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-P…
11184 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duple…
11223 … USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
11280 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud …
11337 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud …
11340 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud …
11495 /* Inter-integrated Circuit Interface (I2C) */
11564 #define I2C_CR1_FMP I2C_CR1_FMP_Msk /*!< Fast-mode Pl…
11581 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit add…
11584 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit add…
11613 …A1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
11775 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit rece…
11780 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit tran…
11785 /* Improved Inter-integrated Circuit Interface (I3C) */
11797 #define I3C_CR_CCC I3C_CR_CCC_Msk /*!< 8-Bit CCC …
11830 #define I3C_CFGR_HKSDAEN I3C_CFGR_HKSDAEN_Msk /*!< High-Keepe…
11985 …ER_DERR_Msk /*!< Data Error during the controller-role hand-off procedure */
11996 … /*!< Target Address Received during accepted IBI or Controller-role request */
12040 … I3C_EVR_CRF_Msk /*!< Controller-role Request Flag */
12043 …DF I3C_EVR_CRUPDF_Msk /*!< Controller-role Update Flag */
12111 … I3C_IER_CRIE_Msk /*!< Controller-role Interrupt Enable…
12114 … I3C_IER_CRUPDIE_Msk /*!< Controller-role Update Interrupt…
12170 …RF I3C_CEVR_CCRF_Msk /*!< Controller-role Clear Flag */
12173 …F I3C_CEVR_CCRUPDF_Msk /*!< Controller-role Update Clear Fla…
12223 …R0_CREN I3C_DEVR0_CREN_Msk /*!< Controller-role Enable */
12250 … I3C_DEVRX_CRACK_Msk /*!< Controller-role Acknowledge from…
12280 … I3C_TIMINGR0_SCLL_PP_Msk /*!< SCL Low duration during I3C Push-Pull phases */
12283 …GR0_SCLH_I3C_Msk /*!< SCL High duration during I3C Open-drain and Push-Pull phases */
12286 …C_TIMINGR0_SCLL_OD_Msk /*!< SCL Low duration during I3C Open-drain phases and I2C …
12363 …HOFF I3C_CRCAPR_CAPDHOFF_Msk /*!< Controller-role handoff needed */
12384 #define I3C_GETMXDSR_TSCO I3C_GETMXDSR_TSCO_Msk /*!< Clock-to-d…
12478 … SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
12484 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC …
12556 …IDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
12644 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet a…
12647 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet s…
12662 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet a…
12803 … WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to L…
12818 … WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
12908 … USB_ISTR_IDN_Msk /*!< EndPoint IDentifier (read-only bit) Mask */
12911 … USB_ISTR_DIR_Msk /*!< DIRection of transaction (read-only bit) Mask */
12917 … USB_ISTR_ESOF_Msk /*!< Expected Start Of Frame (clear-only bit) Mask */
12920 #define USB_ISTR_SOF USB_ISTR_SOF_Msk /*!< Start Of Frame (clear-…
12926 #define USB_ISTR_DCON USB_ISTR_DCON_Msk /*!< HOST MODE-Device Conne…
12929 #define USB_ISTR_SUSP USB_ISTR_SUSP_Msk /*!< SUSPend (clear-only bi…
12932 #define USB_ISTR_WKUP USB_ISTR_WKUP_Msk /*!< WaKe UP (clear-only bi…
12935 #define USB_ISTR_ERR USB_ISTR_ERR_Msk /*!< ERRor (clear-only bit)…
12938 …OVR USB_ISTR_PMAOVR_Msk /*!< PMA OVeR/underrun (clear-only bit) Mask */
12941 …R USB_ISTR_CTR_Msk /*!< Correct TRansfer (clear-only bit) Mask */
12964 #define USB_FNR_RXDM USB_FNR_RXDM_Msk /*!< status of D- data line…
13044 #define USB_BCDR_DPPU USB_BCDR_DPPU_Msk /*!< DP Pull-up Enable Mask…
13047 #define USB_BCDR_DPPD USB_BCDR_DPPD_Msk /*!< DP Pull-Down Enable Ma…
13442 /****************** TIM Instances : supporting combined 3-phase PWM mode ******/
13559 /******************** UART Instances : Half-Duplex mode **********************/
13575 /******************** UART Instances : Wake-up from Stop mode **********************/