662   uint32_t tmpcr2;  in LL_TIM_HALLSENSOR_Init()  local
677   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in LL_TIM_HALLSENSOR_Init()
689   tmpcr2 |= TIM_CR2_TI1S;  in LL_TIM_HALLSENSOR_Init()
692   tmpcr2 |= LL_TIM_TRGO_OC2REF;  in LL_TIM_HALLSENSOR_Init()
715   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in LL_TIM_HALLSENSOR_Init()
846   uint32_t tmpcr2;  in OC1Config()  local
861   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC1Config()
892     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);  in OC1Config()
895     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);  in OC1Config()
899   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC1Config()
925   uint32_t tmpcr2;  in OC2Config()  local
940   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC2Config()
971     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);  in OC2Config()
974     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);  in OC2Config()
978   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC2Config()
1004   uint32_t tmpcr2;  in OC3Config()  local
1019   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC3Config()
1050     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);  in OC3Config()
1053     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);  in OC3Config()
1057   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC3Config()
1083   uint32_t tmpcr2;  in OC4Config()  local
1098   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);  in OC4Config()
1129     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);  in OC4Config()
1132     MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);  in OC4Config()
1136   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC4Config()