Lines Matching refs:tmpccer
570 uint32_t tmpccer; in LL_TIM_ENCODER_Init() local
591 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
606 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_ENCODER_Init()
607 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); in LL_TIM_ENCODER_Init()
608 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); in LL_TIM_ENCODER_Init()
609 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
618 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
664 uint32_t tmpccer; in LL_TIM_HALLSENSOR_Init() local
683 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_HALLSENSOR_Init()
710 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); in LL_TIM_HALLSENSOR_Init()
711 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); in LL_TIM_HALLSENSOR_Init()
712 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_HALLSENSOR_Init()
724 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_HALLSENSOR_Init()
845 uint32_t tmpccer; in OC1Config() local
858 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
873 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); in OC1Config()
876 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); in OC1Config()
886 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); in OC1Config()
889 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); in OC1Config()
908 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
924 uint32_t tmpccer; in OC2Config() local
937 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
952 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); in OC2Config()
955 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); in OC2Config()
965 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); in OC2Config()
968 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); in OC2Config()
987 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
1003 uint32_t tmpccer; in OC3Config() local
1016 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC3Config()
1031 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); in OC3Config()
1034 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); in OC3Config()
1044 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); in OC3Config()
1047 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); in OC3Config()
1066 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC3Config()
1082 uint32_t tmpccer; in OC4Config() local
1095 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC4Config()
1110 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); in OC4Config()
1113 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); in OC4Config()
1123 MODIFY_REG(tmpccer, TIM_CCER_CC4NP, TIM_OCInitStruct->OCNPolarity << 14U); in OC4Config()
1126 MODIFY_REG(tmpccer, TIM_CCER_CC4NE, TIM_OCInitStruct->OCNState << 14U); in OC4Config()
1145 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC4Config()
1161 uint32_t tmpccer; in OC5Config() local
1175 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC5Config()
1184 MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U); in OC5Config()
1187 MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U); in OC5Config()
1206 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC5Config()
1222 uint32_t tmpccer; in OC6Config() local
1236 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC6Config()
1245 MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U); in OC6Config()
1248 MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U); in OC6Config()
1266 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC6Config()