585   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
591   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
618   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
674   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
683   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
724   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
855   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
858   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
908   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
934   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
937   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
987   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
1013   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
1016   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1066   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1092   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1095   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1145   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1172   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1175   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1206   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1233   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1236   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1266   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1289   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1297   MODIFY_REG(TIMx->CCER,  in IC1Config()
1322   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1330   MODIFY_REG(TIMx->CCER,  in IC2Config()
1355   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1363   MODIFY_REG(TIMx->CCER,  in IC3Config()
1388   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1396   MODIFY_REG(TIMx->CCER,  in IC4Config()