Lines Matching refs:Timing
386 const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
392 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
393 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
394 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Timing_Init()
395 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
396 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
397 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
398 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
399 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
404 (Timing->AddressSetupTime << FMC_BTRx_ADDSET_Pos) | in FMC_NORSRAM_Timing_Init()
405 (Timing->AddressHoldTime << FMC_BTRx_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
406 (Timing->DataSetupTime << FMC_BTRx_DATAST_Pos) | in FMC_NORSRAM_Timing_Init()
407 (Timing->DataHoldTime << FMC_BTRx_DATAHLD_Pos) | in FMC_NORSRAM_Timing_Init()
408 (Timing->BusTurnAroundDuration << FMC_BTRx_BUSTURN_Pos) | in FMC_NORSRAM_Timing_Init()
409 ((Timing->CLKDivision - 1U) << FMC_BTRx_CLKDIV_Pos) | in FMC_NORSRAM_Timing_Init()
410 ((Timing->DataLatency - 2U) << FMC_BTRx_DATLAT_Pos) | in FMC_NORSRAM_Timing_Init()
411 Timing->AccessMode; in FMC_NORSRAM_Timing_Init()
417 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
437 … const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, in FMC_NORSRAM_Extended_Timing_Init() argument
448 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
449 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Extended_Timing_Init()
450 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
451 assert_param(IS_FMC_DATAHOLD_DURATION(Timing->DataHoldTime)); in FMC_NORSRAM_Extended_Timing_Init()
452 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Extended_Timing_Init()
453 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Extended_Timing_Init()
457 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
458 … ((Timing->AddressHoldTime) << FMC_BWTRx_ADDHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
459 … ((Timing->DataSetupTime) << FMC_BWTRx_DATAST_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
460 … ((Timing->DataHoldTime) << FMC_BWTRx_DATAHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
461 … Timing->AccessMode | in FMC_NORSRAM_Extended_Timing_Init()
462 … ((Timing->BusTurnAroundDuration) << FMC_BWTRx_BUSTURN_Pos))); in FMC_NORSRAM_Extended_Timing_Init()
619 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_CommonSpace_Timing_Init() argument
623 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
624 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
625 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
626 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
633 Device->PMEM = (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
634 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
635 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
636 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); in FMC_NAND_CommonSpace_Timing_Init()
650 … const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_AttributeSpace_Timing_Init() argument
654 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
655 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
656 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
657 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
664 Device->PATT = (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
665 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
666 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
667 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); in FMC_NAND_AttributeSpace_Timing_Init()
922 const FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_SDRAM_Timing_Init() argument
926 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); in FMC_SDRAM_Timing_Init()
927 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); in FMC_SDRAM_Timing_Init()
928 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); in FMC_SDRAM_Timing_Init()
929 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); in FMC_SDRAM_Timing_Init()
930 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); in FMC_SDRAM_Timing_Init()
931 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); in FMC_SDRAM_Timing_Init()
932 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); in FMC_SDRAM_Timing_Init()
940 (((Timing->LoadToActiveDelay) - 1U) | in FMC_SDRAM_Timing_Init()
941 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) | in FMC_SDRAM_Timing_Init()
942 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) | in FMC_SDRAM_Timing_Init()
943 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) | in FMC_SDRAM_Timing_Init()
944 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) | in FMC_SDRAM_Timing_Init()
945 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos) | in FMC_SDRAM_Timing_Init()
946 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos))); in FMC_SDRAM_Timing_Init()
953 (((Timing->RowCycleDelay) - 1U) << FMC_SDTRx_TRC_Pos) | in FMC_SDRAM_Timing_Init()
954 (((Timing->RPDelay) - 1U) << FMC_SDTRx_TRP_Pos)); in FMC_SDRAM_Timing_Init()
958 (((Timing->LoadToActiveDelay) - 1U) | in FMC_SDRAM_Timing_Init()
959 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTRx_TXSR_Pos) | in FMC_SDRAM_Timing_Init()
960 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTRx_TRAS_Pos) | in FMC_SDRAM_Timing_Init()
961 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTRx_TWR_Pos) | in FMC_SDRAM_Timing_Init()
962 (((Timing->RCDDelay) - 1U) << FMC_SDTRx_TRCD_Pos))); in FMC_SDRAM_Timing_Init()