Lines Matching refs:Init
198 const FMC_NORSRAM_InitTypeDef *Init) in FMC_NORSRAM_Init() argument
206 assert_param(IS_FMC_NORSRAM_BANK(Init->NSBank)); in FMC_NORSRAM_Init()
207 assert_param(IS_FMC_MUX(Init->DataAddressMux)); in FMC_NORSRAM_Init()
208 assert_param(IS_FMC_MEMORY(Init->MemoryType)); in FMC_NORSRAM_Init()
209 assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NORSRAM_Init()
210 assert_param(IS_FMC_BURSTMODE(Init->BurstAccessMode)); in FMC_NORSRAM_Init()
211 assert_param(IS_FMC_WAIT_POLARITY(Init->WaitSignalPolarity)); in FMC_NORSRAM_Init()
212 assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive)); in FMC_NORSRAM_Init()
213 assert_param(IS_FMC_WRITE_OPERATION(Init->WriteOperation)); in FMC_NORSRAM_Init()
214 assert_param(IS_FMC_WAITE_SIGNAL(Init->WaitSignal)); in FMC_NORSRAM_Init()
215 assert_param(IS_FMC_EXTENDED_MODE(Init->ExtendedMode)); in FMC_NORSRAM_Init()
216 assert_param(IS_FMC_ASYNWAIT(Init->AsynchronousWait)); in FMC_NORSRAM_Init()
217 assert_param(IS_FMC_WRITE_BURST(Init->WriteBurst)); in FMC_NORSRAM_Init()
218 assert_param(IS_FMC_CONTINOUS_CLOCK(Init->ContinuousClock)); in FMC_NORSRAM_Init()
219 assert_param(IS_FMC_WRITE_FIFO(Init->WriteFifo)); in FMC_NORSRAM_Init()
220 assert_param(IS_FMC_PAGESIZE(Init->PageSize)); in FMC_NORSRAM_Init()
221 assert_param(IS_FMC_NBL_SETUPTIME(Init->NBLSetupTime)); in FMC_NORSRAM_Init()
222 assert_param(IS_FUNCTIONAL_STATE(Init->MaxChipSelectPulse)); in FMC_NORSRAM_Init()
225 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
228 if (Init->MemoryType == FMC_MEMORY_TYPE_NOR) in FMC_NORSRAM_Init()
238 Init->DataAddressMux | \ in FMC_NORSRAM_Init()
239 Init->MemoryType | \ in FMC_NORSRAM_Init()
240 Init->MemoryDataWidth | \ in FMC_NORSRAM_Init()
241 Init->BurstAccessMode | \ in FMC_NORSRAM_Init()
242 Init->WaitSignalPolarity | \ in FMC_NORSRAM_Init()
243 Init->WaitSignalActive | \ in FMC_NORSRAM_Init()
244 Init->WriteOperation | \ in FMC_NORSRAM_Init()
245 Init->WaitSignal | \ in FMC_NORSRAM_Init()
246 Init->ExtendedMode | \ in FMC_NORSRAM_Init()
247 Init->AsynchronousWait | \ in FMC_NORSRAM_Init()
248 Init->WriteBurst); in FMC_NORSRAM_Init()
250 btcr_reg |= Init->ContinuousClock; in FMC_NORSRAM_Init()
251 btcr_reg |= Init->WriteFifo; in FMC_NORSRAM_Init()
252 btcr_reg |= Init->NBLSetupTime; in FMC_NORSRAM_Init()
253 btcr_reg |= Init->PageSize; in FMC_NORSRAM_Init()
274 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
277 …if ((Init->ContinuousClock == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC) && (Init->NSBank != FMC_NORSRAM_BAN… in FMC_NORSRAM_Init()
279 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
282 if (Init->NSBank != FMC_NORSRAM_BANK1) in FMC_NORSRAM_Init()
285 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
289 if (Init->MaxChipSelectPulse == ENABLE) in FMC_NORSRAM_Init()
292 assert_param(IS_FMC_MAX_CHIP_SELECT_PULSE_TIME(Init->MaxChipSelectPulseTime)); in FMC_NORSRAM_Init()
295 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); in FMC_NORSRAM_Init()
298 switch (Init->NSBank) in FMC_NORSRAM_Init()
586 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) in FMC_NAND_Init() argument
590 assert_param(IS_FMC_NAND_BANK(Init->NandBank)); in FMC_NAND_Init()
591 assert_param(IS_FMC_WAIT_FEATURE(Init->Waitfeature)); in FMC_NAND_Init()
592 assert_param(IS_FMC_NAND_MEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_NAND_Init()
593 assert_param(IS_FMC_ECC_STATE(Init->EccComputation)); in FMC_NAND_Init()
594 assert_param(IS_FMC_ECCPAGE_SIZE(Init->ECCPageSize)); in FMC_NAND_Init()
595 assert_param(IS_FMC_TCLR_TIME(Init->TCLRSetupTime)); in FMC_NAND_Init()
596 assert_param(IS_FMC_TAR_TIME(Init->TARSetupTime)); in FMC_NAND_Init()
599 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
601 Init->MemoryDataWidth | in FMC_NAND_Init()
602 Init->EccComputation | in FMC_NAND_Init()
603 Init->ECCPageSize | in FMC_NAND_Init()
604 ((Init->TCLRSetupTime) << FMC_PCR_TCLR_Pos) | in FMC_NAND_Init()
605 ((Init->TARSetupTime) << FMC_PCR_TAR_Pos))); in FMC_NAND_Init()
859 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) in FMC_SDRAM_Init() argument
863 assert_param(IS_FMC_SDRAM_BANK(Init->SDBank)); in FMC_SDRAM_Init()
864 assert_param(IS_FMC_COLUMNBITS_NUMBER(Init->ColumnBitsNumber)); in FMC_SDRAM_Init()
865 assert_param(IS_FMC_ROWBITS_NUMBER(Init->RowBitsNumber)); in FMC_SDRAM_Init()
866 assert_param(IS_FMC_SDMEMORY_WIDTH(Init->MemoryDataWidth)); in FMC_SDRAM_Init()
867 assert_param(IS_FMC_INTERNALBANK_NUMBER(Init->InternalBankNumber)); in FMC_SDRAM_Init()
868 assert_param(IS_FMC_CAS_LATENCY(Init->CASLatency)); in FMC_SDRAM_Init()
869 assert_param(IS_FMC_WRITE_PROTECTION(Init->WriteProtection)); in FMC_SDRAM_Init()
870 assert_param(IS_FMC_SDCLOCK_PERIOD(Init->SDClockPeriod)); in FMC_SDRAM_Init()
871 assert_param(IS_FMC_READ_BURST(Init->ReadBurst)); in FMC_SDRAM_Init()
872 assert_param(IS_FMC_READPIPE_DELAY(Init->ReadPipeDelay)); in FMC_SDRAM_Init()
875 if (Init->SDBank == FMC_SDRAM_BANK1) in FMC_SDRAM_Init()
879 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
880 Init->RowBitsNumber | in FMC_SDRAM_Init()
881 Init->MemoryDataWidth | in FMC_SDRAM_Init()
882 Init->InternalBankNumber | in FMC_SDRAM_Init()
883 Init->CASLatency | in FMC_SDRAM_Init()
884 Init->WriteProtection | in FMC_SDRAM_Init()
885 Init->SDClockPeriod | in FMC_SDRAM_Init()
886 Init->ReadBurst | in FMC_SDRAM_Init()
887 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
895 (Init->SDClockPeriod | in FMC_SDRAM_Init()
896 Init->ReadBurst | in FMC_SDRAM_Init()
897 Init->ReadPipeDelay)); in FMC_SDRAM_Init()
901 (Init->ColumnBitsNumber | in FMC_SDRAM_Init()
902 Init->RowBitsNumber | in FMC_SDRAM_Init()
903 Init->MemoryDataWidth | in FMC_SDRAM_Init()
904 Init->InternalBankNumber | in FMC_SDRAM_Init()
905 Init->CASLatency | in FMC_SDRAM_Init()
906 Init->WriteProtection)); in FMC_SDRAM_Init()