Lines Matching refs:Device
197 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Init() argument
205 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Init()
225 __FMC_NORSRAM_DISABLE(Device, Init->NSBank); in FMC_NORSRAM_Init()
274 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
279 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
285 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
295 MODIFY_REG(Device->PCSCNTR, FMC_PCSCNTR_CSCOUNT, (uint32_t)(Init->MaxChipSelectPulseTime)); in FMC_NORSRAM_Init()
301 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); in FMC_NORSRAM_Init()
305 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); in FMC_NORSRAM_Init()
309 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); in FMC_NORSRAM_Init()
313 SET_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); in FMC_NORSRAM_Init()
328 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_DeInit() argument
332 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_DeInit()
337 __FMC_NORSRAM_DISABLE(Device, Bank); in FMC_NORSRAM_DeInit()
343 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
348 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
351 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
358 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB1EN); in FMC_NORSRAM_DeInit()
362 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB2EN); in FMC_NORSRAM_DeInit()
366 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB3EN); in FMC_NORSRAM_DeInit()
370 CLEAR_BIT(Device->PCSCNTR, FMC_PCSCNTR_CNTB4EN); in FMC_NORSRAM_DeInit()
385 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, in FMC_NORSRAM_Timing_Init() argument
391 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_Timing_Init()
403 Device->BTCR[Bank + 1U] = in FMC_NORSRAM_Timing_Init()
414 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
416 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
418 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
436 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, in FMC_NORSRAM_Extended_Timing_Init() argument
447 assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device)); in FMC_NORSRAM_Extended_Timing_Init()
457 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
466 Device->BWTR[Bank] = 0x0FFFFFFFU; in FMC_NORSRAM_Extended_Timing_Init()
496 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) in FMC_NORSRAM_WriteOperation_Enable() argument
499 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_WriteOperation_Enable()
503 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Enable()
514 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank) in FMC_NORSRAM_WriteOperation_Disable() argument
517 assert_param(IS_FMC_NORSRAM_DEVICE(Device)); in FMC_NORSRAM_WriteOperation_Disable()
521 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Disable()
586 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) in FMC_NAND_Init() argument
589 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_Init()
599 MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature | in FMC_NAND_Init()
618 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, in FMC_NAND_CommonSpace_Timing_Init() argument
622 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_CommonSpace_Timing_Init()
633 Device->PMEM = (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
649 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, in FMC_NAND_AttributeSpace_Timing_Init() argument
653 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_AttributeSpace_Timing_Init()
664 Device->PATT = (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
678 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_DeInit() argument
681 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_DeInit()
685 __FMC_NAND_DISABLE(Device, Bank); in FMC_NAND_DeInit()
692 WRITE_REG(Device->PCR, 0x00000018U); in FMC_NAND_DeInit()
693 WRITE_REG(Device->SR, 0x00000040U); in FMC_NAND_DeInit()
694 WRITE_REG(Device->PMEM, 0xFCFCFCFCU); in FMC_NAND_DeInit()
695 WRITE_REG(Device->PATT, 0xFCFCFCFCU); in FMC_NAND_DeInit()
726 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_ECC_Enable() argument
729 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_ECC_Enable()
736 SET_BIT(Device->PCR, FMC_PCR_ECCEN); in FMC_NAND_ECC_Enable()
748 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) in FMC_NAND_ECC_Disable() argument
751 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_ECC_Disable()
758 CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN); in FMC_NAND_ECC_Disable()
771 HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, in FMC_NAND_GetECC() argument
777 assert_param(IS_FMC_NAND_DEVICE(Device)); in FMC_NAND_GetECC()
784 while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET) in FMC_NAND_GetECC()
800 *ECCval = (uint32_t)Device->ECCR; in FMC_NAND_GetECC()
859 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, const FMC_SDRAM_InitTypeDef *Init) in FMC_SDRAM_Init() argument
862 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_Init()
877 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
891 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1], in FMC_SDRAM_Init()
899 MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2], in FMC_SDRAM_Init()
921 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_Timing_Init() argument
925 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_Timing_Init()
938 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
950 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1], in FMC_SDRAM_Timing_Init()
956 MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2], in FMC_SDRAM_Timing_Init()
973 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_DeInit() argument
976 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_DeInit()
980 Device->SDCR[Bank] = 0x000002D0U; in FMC_SDRAM_DeInit()
981 Device->SDTR[Bank] = 0x0FFFFFFFU; in FMC_SDRAM_DeInit()
982 Device->SDCMR = 0x00000000U; in FMC_SDRAM_DeInit()
983 Device->SDRTR = 0x00000000U; in FMC_SDRAM_DeInit()
984 Device->SDSR = 0x00000000U; in FMC_SDRAM_DeInit()
1014 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_WriteProtection_Enable() argument
1017 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_WriteProtection_Enable()
1021 SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Enable()
1031 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_WriteProtection_Disable() argument
1034 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_WriteProtection_Disable()
1038 CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE); in FMC_SDRAM_WriteProtection_Disable()
1051 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_SendCommand() argument
1055 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_SendCommand()
1062 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC… in FMC_SDRAM_SendCommand()
1077 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate) in FMC_SDRAM_ProgramRefreshRate() argument
1080 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_ProgramRefreshRate()
1084 MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos)); in FMC_SDRAM_ProgramRefreshRate()
1095 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, in FMC_SDRAM_SetAutoRefreshNumber() argument
1099 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_SetAutoRefreshNumber()
1103 MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos)); in FMC_SDRAM_SetAutoRefreshNumber()
1117 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank) in FMC_SDRAM_GetModeStatus() argument
1122 assert_param(IS_FMC_SDRAM_DEVICE(Device)); in FMC_SDRAM_GetModeStatus()
1128 tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1); in FMC_SDRAM_GetModeStatus()
1132 tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U); in FMC_SDRAM_GetModeStatus()