Lines Matching refs:BTCR
274 MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg); in FMC_NORSRAM_Init()
279 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock); in FMC_NORSRAM_Init()
285 SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo)); in FMC_NORSRAM_Init()
343 Device->BTCR[Bank] = 0x000030DBU; in FMC_NORSRAM_DeInit()
348 Device->BTCR[Bank] = 0x000030D2U; in FMC_NORSRAM_DeInit()
351 Device->BTCR[Bank + 1U] = 0x0FFFFFFFU; in FMC_NORSRAM_DeInit()
403 Device->BTCR[Bank + 1U] = in FMC_NORSRAM_Timing_Init()
414 if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) in FMC_NORSRAM_Timing_Init()
416 tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); in FMC_NORSRAM_Timing_Init()
418 MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); in FMC_NORSRAM_Timing_Init()
503 SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Enable()
521 CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE); in FMC_NORSRAM_WriteOperation_Disable()