Lines Matching refs:hxspi
288 static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, F…
290 static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pC…
323 HAL_StatusTypeDef HAL_XSPI_Init(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_Init() argument
329 if (hxspi == NULL) in HAL_XSPI_Init()
337 assert_param(IS_XSPI_MEMORY_MODE(hxspi->Init.MemoryMode)); in HAL_XSPI_Init()
338 assert_param(IS_XSPI_MEMORY_TYPE(hxspi->Init.MemoryType)); in HAL_XSPI_Init()
339 assert_param(IS_XSPI_MEMORY_SIZE(hxspi->Init.MemorySize)); in HAL_XSPI_Init()
340 assert_param(IS_XSPI_CS_HIGH_TIME_CYCLE(hxspi->Init.ChipSelectHighTimeCycle)); in HAL_XSPI_Init()
341 assert_param(IS_XSPI_FREE_RUN_CLK(hxspi->Init.FreeRunningClock)); in HAL_XSPI_Init()
342 assert_param(IS_XSPI_CLOCK_MODE(hxspi->Init.ClockMode)); in HAL_XSPI_Init()
343 assert_param(IS_XSPI_WRAP_SIZE(hxspi->Init.WrapSize)); in HAL_XSPI_Init()
344 assert_param(IS_XSPI_CLK_PRESCALER(hxspi->Init.ClockPrescaler)); in HAL_XSPI_Init()
345 assert_param(IS_XSPI_SAMPLE_SHIFTING(hxspi->Init.SampleShifting)); in HAL_XSPI_Init()
346 assert_param(IS_XSPI_DHQC(hxspi->Init.DelayHoldQuarterCycle)); in HAL_XSPI_Init()
347 assert_param(IS_XSPI_CS_BOUND(hxspi->Init.ChipSelectBoundary)); in HAL_XSPI_Init()
348 assert_param(IS_XSPI_FIFO_THRESHOLD_BYTE(hxspi->Init.FifoThresholdByte)); in HAL_XSPI_Init()
349 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
351 assert_param(IS_XSPI_DLYB_BYPASS(hxspi->Init.DelayBlockBypass)); in HAL_XSPI_Init()
354 hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; in HAL_XSPI_Init()
357 if (hxspi->State == HAL_XSPI_STATE_RESET) in HAL_XSPI_Init()
361 hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; in HAL_XSPI_Init()
362 hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; in HAL_XSPI_Init()
363 hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; in HAL_XSPI_Init()
364 hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; in HAL_XSPI_Init()
365 hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; in HAL_XSPI_Init()
366 hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; in HAL_XSPI_Init()
367 hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; in HAL_XSPI_Init()
368 hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; in HAL_XSPI_Init()
369 hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; in HAL_XSPI_Init()
370 hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; in HAL_XSPI_Init()
372 if (hxspi->MspInitCallback == NULL) in HAL_XSPI_Init()
374 hxspi->MspInitCallback = HAL_XSPI_MspInit; in HAL_XSPI_Init()
378 hxspi->MspInitCallback(hxspi); in HAL_XSPI_Init()
381 HAL_XSPI_MspInit(hxspi); in HAL_XSPI_Init()
385 (void)HAL_XSPI_SetTimeout(hxspi, HAL_XSPI_TIMEOUT_DEFAULT_VALUE); in HAL_XSPI_Init()
388 MODIFY_REG(hxspi->Instance->DCR1, in HAL_XSPI_Init()
390 (hxspi->Init.MemoryType | ((hxspi->Init.MemorySize) << XSPI_DCR1_DEVSIZE_Pos) | in HAL_XSPI_Init()
391 … ((hxspi->Init.ChipSelectHighTimeCycle - 1U) << XSPI_DCR1_CSHT_Pos) | hxspi->Init.ClockMode)); in HAL_XSPI_Init()
394 if (IS_OSPI_ALL_INSTANCE(hxspi->Instance)) in HAL_XSPI_Init()
396 MODIFY_REG(hxspi->Instance->DCR1, OCTOSPI_DCR1_DLYBYP, hxspi->Init.DelayBlockBypass); in HAL_XSPI_Init()
400 MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_WRAPSIZE, hxspi->Init.WrapSize); in HAL_XSPI_Init()
403 …MODIFY_REG(hxspi->Instance->DCR3, XSPI_DCR3_CSBOUND, (hxspi->Init.ChipSelectBoundary << XSPI_DCR3_… in HAL_XSPI_Init()
406 hxspi->Instance->DCR4 = hxspi->Init.Refresh; in HAL_XSPI_Init()
409 …MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_F… in HAL_XSPI_Init()
412 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Init()
417 MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, in HAL_XSPI_Init()
418 ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); in HAL_XSPI_Init()
421 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_DMM, hxspi->Init.MemoryMode); in HAL_XSPI_Init()
424 MODIFY_REG(hxspi->Instance->TCR, (XSPI_TCR_SSHIFT | XSPI_TCR_DHQC), in HAL_XSPI_Init()
425 (hxspi->Init.SampleShifting | hxspi->Init.DelayHoldQuarterCycle)); in HAL_XSPI_Init()
428 HAL_XSPI_ENABLE(hxspi); in HAL_XSPI_Init()
431 if (hxspi->Init.FreeRunningClock == HAL_XSPI_FREERUNCLK_ENABLE) in HAL_XSPI_Init()
433 SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_Init()
437 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Init()
439 hxspi->State = HAL_XSPI_STATE_HYPERBUS_INIT; in HAL_XSPI_Init()
443 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Init()
456 __weak void HAL_XSPI_MspInit(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_MspInit() argument
459 UNUSED(hxspi); in HAL_XSPI_MspInit()
471 HAL_StatusTypeDef HAL_XSPI_DeInit(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_DeInit() argument
476 if (hxspi == NULL) in HAL_XSPI_DeInit()
484 HAL_XSPI_DISABLE(hxspi); in HAL_XSPI_DeInit()
487 CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DeInit()
490 if (hxspi->MspDeInitCallback == NULL) in HAL_XSPI_DeInit()
492 hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; in HAL_XSPI_DeInit()
496 hxspi->MspDeInitCallback(hxspi); in HAL_XSPI_DeInit()
499 HAL_XSPI_MspDeInit(hxspi); in HAL_XSPI_DeInit()
503 hxspi->State = HAL_XSPI_STATE_RESET; in HAL_XSPI_DeInit()
514 __weak void HAL_XSPI_MspDeInit(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_MspDeInit() argument
517 UNUSED(hxspi); in HAL_XSPI_MspDeInit()
554 void HAL_XSPI_IRQHandler(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_IRQHandler() argument
556 __IO uint32_t *data_reg = &hxspi->Instance->DR; in HAL_XSPI_IRQHandler()
557 uint32_t flag = hxspi->Instance->SR; in HAL_XSPI_IRQHandler()
558 uint32_t itsource = hxspi->Instance->CR; in HAL_XSPI_IRQHandler()
559 uint32_t currentstate = hxspi->State; in HAL_XSPI_IRQHandler()
567 *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; in HAL_XSPI_IRQHandler()
568 hxspi->pBuffPtr++; in HAL_XSPI_IRQHandler()
569 hxspi->XferCount--; in HAL_XSPI_IRQHandler()
574 *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); in HAL_XSPI_IRQHandler()
575 hxspi->pBuffPtr++; in HAL_XSPI_IRQHandler()
576 hxspi->XferCount--; in HAL_XSPI_IRQHandler()
583 if (hxspi->XferCount == 0U) in HAL_XSPI_IRQHandler()
587 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_FT); in HAL_XSPI_IRQHandler()
592 hxspi->FifoThresholdCallback(hxspi); in HAL_XSPI_IRQHandler()
594 HAL_XSPI_FifoThresholdCallback(hxspi); in HAL_XSPI_IRQHandler()
602 if ((hxspi->XferCount > 0U) && ((flag & XSPI_SR_FLEVEL) != 0U)) in HAL_XSPI_IRQHandler()
605 *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); in HAL_XSPI_IRQHandler()
606 hxspi->pBuffPtr++; in HAL_XSPI_IRQHandler()
607 hxspi->XferCount--; in HAL_XSPI_IRQHandler()
609 else if (hxspi->XferCount == 0U) in HAL_XSPI_IRQHandler()
612 hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; in HAL_XSPI_IRQHandler()
615 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_IRQHandler()
617 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
621 hxspi->RxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
623 HAL_XSPI_RxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
634 hxspi->Instance->FCR = HAL_XSPI_FLAG_TC; in HAL_XSPI_IRQHandler()
637 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_IRQHandler()
639 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
645 hxspi->TxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
647 HAL_XSPI_TxCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
654 hxspi->CmdCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
656 HAL_XSPI_CmdCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
661 if (hxspi->ErrorCode == HAL_XSPI_ERROR_NONE) in HAL_XSPI_IRQHandler()
666 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
668 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_IRQHandler()
676 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
678 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
692 hxspi->Instance->FCR = HAL_XSPI_FLAG_SM; in HAL_XSPI_IRQHandler()
695 if ((hxspi->Instance->CR & XSPI_CR_APMS) != 0U) in HAL_XSPI_IRQHandler()
698 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); in HAL_XSPI_IRQHandler()
700 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
705 hxspi->StatusMatchCallback(hxspi); in HAL_XSPI_IRQHandler()
707 HAL_XSPI_StatusMatchCallback(hxspi); in HAL_XSPI_IRQHandler()
714 hxspi->Instance->FCR = HAL_XSPI_FLAG_TE; in HAL_XSPI_IRQHandler()
717 …HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HA… in HAL_XSPI_IRQHandler()
720 hxspi->ErrorCode = HAL_XSPI_ERROR_TRANSFER; in HAL_XSPI_IRQHandler()
723 if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) in HAL_XSPI_IRQHandler()
726 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_IRQHandler()
729 hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_IRQHandler()
730 if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) in HAL_XSPI_IRQHandler()
732 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
736 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
738 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
743 hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_IRQHandler()
744 if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) in HAL_XSPI_IRQHandler()
746 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
750 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
752 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
758 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_IRQHandler()
762 hxspi->ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
764 HAL_XSPI_ErrorCallback(hxspi); in HAL_XSPI_IRQHandler()
772 hxspi->Instance->FCR = HAL_XSPI_FLAG_TO; in HAL_XSPI_IRQHandler()
776 hxspi->TimeOutCallback(hxspi); in HAL_XSPI_IRQHandler()
778 HAL_XSPI_TimeOutCallback(hxspi); in HAL_XSPI_IRQHandler()
794 HAL_StatusTypeDef HAL_XSPI_Command(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd, u… in HAL_XSPI_Command() argument
802 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in HAL_XSPI_Command()
844 state = hxspi->State; in HAL_XSPI_Command()
845 …if (((state == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERB… in HAL_XSPI_Command()
853 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_Command()
858 hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; in HAL_XSPI_Command()
861 status = XSPI_ConfigCmd(hxspi, pCmd); in HAL_XSPI_Command()
869 … status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_Command()
872 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Command()
879 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_Command()
883 if (hxspi->State == HAL_XSPI_STATE_WRITE_CMD_CFG) in HAL_XSPI_Command()
885 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_Command()
889 hxspi->State = HAL_XSPI_STATE_READ_CMD_CFG; in HAL_XSPI_Command()
894 if (hxspi->State == HAL_XSPI_STATE_READ_CMD_CFG) in HAL_XSPI_Command()
896 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_Command()
900 hxspi->State = HAL_XSPI_STATE_WRITE_CMD_CFG; in HAL_XSPI_Command()
918 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Command()
931 HAL_StatusTypeDef HAL_XSPI_Command_IT(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *const pCmd) in HAL_XSPI_Command_IT() argument
939 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in HAL_XSPI_Command_IT()
978 …if ((hxspi->State == HAL_XSPI_STATE_READY) && (pCmd->OperationType == HAL_XSPI_OPTYPE_COMMON_… in HAL_XSPI_Command_IT()
979 … (pCmd->DataMode == HAL_XSPI_DATA_NONE) && (hxspi->Init.MemoryType != HAL_XSPI_MEMTYPE_HYPERBUS)) in HAL_XSPI_Command_IT()
982 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Command_IT()
987 hxspi->ErrorCode = HAL_XSPI_ERROR_NONE; in HAL_XSPI_Command_IT()
990 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Command_IT()
993 status = XSPI_ConfigCmd(hxspi, pCmd); in HAL_XSPI_Command_IT()
998 hxspi->State = HAL_XSPI_STATE_BUSY_CMD; in HAL_XSPI_Command_IT()
1001 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_TE); in HAL_XSPI_Command_IT()
1008 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Command_IT()
1021 HAL_StatusTypeDef HAL_XSPI_HyperbusCfg(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCfgTypeDef *const pC… in HAL_XSPI_HyperbusCfg() argument
1035 state = hxspi->State; in HAL_XSPI_HyperbusCfg()
1039 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_HyperbusCfg()
1044 WRITE_REG(hxspi->Instance->HLCR, ((pCfg->RWRecoveryTimeCycle << XSPI_HLCR_TRWR_Pos) | in HAL_XSPI_HyperbusCfg()
1049 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_HyperbusCfg()
1059 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_HyperbusCfg()
1072 HAL_StatusTypeDef HAL_XSPI_HyperbusCmd(XSPI_HandleTypeDef *hxspi, XSPI_HyperbusCmdTypeDef *const pC… in HAL_XSPI_HyperbusCmd() argument
1085 …if ((hxspi->State == HAL_XSPI_STATE_READY) && (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS… in HAL_XSPI_HyperbusCmd()
1088 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_HyperbusCmd()
1093 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); in HAL_XSPI_HyperbusCmd()
1096 MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP_0, pCmd->AddressSpace); in HAL_XSPI_HyperbusCmd()
1102 WRITE_REG(hxspi->Instance->CCR, (pCmd->DQSMode | XSPI_CCR_DDTR | XSPI_CCR_DMODE_2 | in HAL_XSPI_HyperbusCmd()
1104 WRITE_REG(hxspi->Instance->WCCR, (pCmd->DQSMode | XSPI_WCCR_DDTR | XSPI_WCCR_DMODE_2 | in HAL_XSPI_HyperbusCmd()
1108 WRITE_REG(hxspi->Instance->DLR, (pCmd->DataLength - 1U)); in HAL_XSPI_HyperbusCmd()
1111 WRITE_REG(hxspi->Instance->AR, pCmd->Address); in HAL_XSPI_HyperbusCmd()
1114 hxspi->State = HAL_XSPI_STATE_CMD_CFG; in HAL_XSPI_HyperbusCmd()
1124 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_HyperbusCmd()
1138 HAL_StatusTypeDef HAL_XSPI_Transmit(XSPI_HandleTypeDef *hxspi, const uint8_t *pData, uint32_t Timeo… in HAL_XSPI_Transmit() argument
1142 __IO uint32_t *data_reg = &hxspi->Instance->DR; in HAL_XSPI_Transmit()
1148 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit()
1153 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Transmit()
1156 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Transmit()
1157 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Transmit()
1158 hxspi->pBuffPtr = (uint8_t *)pData; in HAL_XSPI_Transmit()
1161 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_XSPI_Transmit()
1166 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_FT, SET, tickstart, Timeout); in HAL_XSPI_Transmit()
1173 *((__IO uint8_t *)data_reg) = *hxspi->pBuffPtr; in HAL_XSPI_Transmit()
1174 hxspi->pBuffPtr++; in HAL_XSPI_Transmit()
1175 hxspi->XferCount--; in HAL_XSPI_Transmit()
1176 } while (hxspi->XferCount > 0U); in HAL_XSPI_Transmit()
1181 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_XSPI_Transmit()
1186 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Transmit()
1188 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Transmit()
1195 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Transmit()
1210 HAL_StatusTypeDef HAL_XSPI_Receive(XSPI_HandleTypeDef *hxspi, uint8_t *const pData, uint32_t Timeou… in HAL_XSPI_Receive() argument
1214 __IO uint32_t *data_reg = &hxspi->Instance->DR; in HAL_XSPI_Receive()
1215 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_Receive()
1216 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_Receive()
1222 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive()
1227 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Receive()
1230 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Receive()
1231 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Receive()
1232 hxspi->pBuffPtr = pData; in HAL_XSPI_Receive()
1235 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_XSPI_Receive()
1238 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Receive()
1240 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive()
1244 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_Receive()
1246 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive()
1250 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_Receive()
1257 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, (HAL_XSPI_FLAG_FT | HAL_XSPI_FLAG_TC), SET, ticksta… in HAL_XSPI_Receive()
1264 *hxspi->pBuffPtr = *((__IO uint8_t *)data_reg); in HAL_XSPI_Receive()
1265 hxspi->pBuffPtr++; in HAL_XSPI_Receive()
1266 hxspi->XferCount--; in HAL_XSPI_Receive()
1267 } while (hxspi->XferCount > 0U); in HAL_XSPI_Receive()
1272 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_XSPI_Receive()
1277 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Receive()
1279 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Receive()
1286 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Receive()
1300 HAL_StatusTypeDef HAL_XSPI_Transmit_IT(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) in HAL_XSPI_Transmit_IT() argument
1308 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_IT()
1313 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Transmit_IT()
1316 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Transmit_IT()
1317 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Transmit_IT()
1318 hxspi->pBuffPtr = (uint8_t *)pData; in HAL_XSPI_Transmit_IT()
1321 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_XSPI_Transmit_IT()
1324 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Transmit_IT()
1327 hxspi->State = HAL_XSPI_STATE_BUSY_TX; in HAL_XSPI_Transmit_IT()
1330 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_Transmit_IT()
1335 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Transmit_IT()
1349 HAL_StatusTypeDef HAL_XSPI_Receive_IT(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) in HAL_XSPI_Receive_IT() argument
1352 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_Receive_IT()
1353 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_Receive_IT()
1359 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_IT()
1364 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Receive_IT()
1367 hxspi->XferCount = READ_REG(hxspi->Instance->DLR) + 1U; in HAL_XSPI_Receive_IT()
1368 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Receive_IT()
1369 hxspi->pBuffPtr = pData; in HAL_XSPI_Receive_IT()
1372 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_XSPI_Receive_IT()
1375 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Receive_IT()
1378 hxspi->State = HAL_XSPI_STATE_BUSY_RX; in HAL_XSPI_Receive_IT()
1381 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in HAL_XSPI_Receive_IT()
1384 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Receive_IT()
1386 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_IT()
1390 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_Receive_IT()
1392 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_IT()
1396 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_Receive_IT()
1403 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Receive_IT()
1421 HAL_StatusTypeDef HAL_XSPI_Transmit_DMA(XSPI_HandleTypeDef *hxspi, const uint8_t *pData) in HAL_XSPI_Transmit_DMA() argument
1424 uint32_t data_size = hxspi->Instance->DLR + 1U; in HAL_XSPI_Transmit_DMA()
1432 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1437 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Transmit_DMA()
1439 if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Transmit_DMA()
1441 p_queue = hxspi->hdmatx->LinkedListQueue; in HAL_XSPI_Transmit_DMA()
1449 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Transmit_DMA()
1457 data_width = hxspi->hdmatx->Init.DestDataWidth; in HAL_XSPI_Transmit_DMA()
1462 hxspi->XferCount = data_size; in HAL_XSPI_Transmit_DMA()
1466 if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) in HAL_XSPI_Transmit_DMA()
1470 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1475 hxspi->XferCount = data_size; in HAL_XSPI_Transmit_DMA()
1480 if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) in HAL_XSPI_Transmit_DMA()
1484 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1489 hxspi->XferCount = data_size; in HAL_XSPI_Transmit_DMA()
1499 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Transmit_DMA()
1500 hxspi->pBuffPtr = (uint8_t *)pData; in HAL_XSPI_Transmit_DMA()
1503 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_XSPI_Transmit_DMA()
1506 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Transmit_DMA()
1509 hxspi->State = HAL_XSPI_STATE_BUSY_TX; in HAL_XSPI_Transmit_DMA()
1512 hxspi->hdmatx->XferCpltCallback = XSPI_DMACplt; in HAL_XSPI_Transmit_DMA()
1515 hxspi->hdmatx->XferHalfCpltCallback = XSPI_DMAHalfCplt; in HAL_XSPI_Transmit_DMA()
1518 hxspi->hdmatx->XferErrorCallback = XSPI_DMAError; in HAL_XSPI_Transmit_DMA()
1521 hxspi->hdmatx->XferAbortCallback = NULL; in HAL_XSPI_Transmit_DMA()
1524 if ((hxspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Transmit_DMA()
1526 if (hxspi->hdmatx->LinkedListQueue != NULL) in HAL_XSPI_Transmit_DMA()
1534 p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; in HAL_XSPI_Transmit_DMA()
1538 p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; in HAL_XSPI_Transmit_DMA()
1540 status = HAL_DMAEx_List_Start_IT(hxspi->hdmatx); in HAL_XSPI_Transmit_DMA()
1545 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Transmit_DMA()
1547 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Transmit_DMA()
1555 if ((hxspi->hdmatx->Init.Direction == DMA_MEMORY_TO_PERIPH) && in HAL_XSPI_Transmit_DMA()
1556 …(hxspi->hdmatx->Init.SrcInc == DMA_SINC_INCREMENTED) && (hxspi->hdmatx->Init.DestInc == DMA_DINC_F… in HAL_XSPI_Transmit_DMA()
1558 …status = HAL_DMA_Start_IT(hxspi->hdmatx, (uint32_t)pData, (uint32_t)&hxspi->Instance->DR, hxspi->X… in HAL_XSPI_Transmit_DMA()
1563 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Transmit_DMA()
1570 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); in HAL_XSPI_Transmit_DMA()
1573 SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Transmit_DMA()
1578 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Transmit_DMA()
1579 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Transmit_DMA()
1586 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Transmit_DMA()
1604 HAL_StatusTypeDef HAL_XSPI_Receive_DMA(XSPI_HandleTypeDef *hxspi, uint8_t *const pData) in HAL_XSPI_Receive_DMA() argument
1607 uint32_t data_size = hxspi->Instance->DLR + 1U; in HAL_XSPI_Receive_DMA()
1608 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_Receive_DMA()
1609 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_Receive_DMA()
1617 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1622 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_Receive_DMA()
1624 if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Receive_DMA()
1626 p_queue = hxspi->hdmarx->LinkedListQueue; in HAL_XSPI_Receive_DMA()
1634 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Receive_DMA()
1642 data_width = hxspi->hdmarx->Init.DestDataWidth; in HAL_XSPI_Receive_DMA()
1648 hxspi->XferCount = data_size; in HAL_XSPI_Receive_DMA()
1652 if (((data_size % 2U) != 0U) || ((hxspi->Init.FifoThresholdByte % 2U) != 0U)) in HAL_XSPI_Receive_DMA()
1656 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1661 hxspi->XferCount = data_size; in HAL_XSPI_Receive_DMA()
1666 if (((data_size % 4U) != 0U) || ((hxspi->Init.FifoThresholdByte % 4U) != 0U)) in HAL_XSPI_Receive_DMA()
1670 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1675 hxspi->XferCount = data_size; in HAL_XSPI_Receive_DMA()
1685 hxspi->XferSize = hxspi->XferCount; in HAL_XSPI_Receive_DMA()
1686 hxspi->pBuffPtr = pData; in HAL_XSPI_Receive_DMA()
1689 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, XSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_XSPI_Receive_DMA()
1692 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_TC); in HAL_XSPI_Receive_DMA()
1695 hxspi->State = HAL_XSPI_STATE_BUSY_RX; in HAL_XSPI_Receive_DMA()
1698 hxspi->hdmarx->XferCpltCallback = XSPI_DMACplt; in HAL_XSPI_Receive_DMA()
1701 hxspi->hdmarx->XferHalfCpltCallback = XSPI_DMAHalfCplt; in HAL_XSPI_Receive_DMA()
1704 hxspi->hdmarx->XferErrorCallback = XSPI_DMAError; in HAL_XSPI_Receive_DMA()
1707 hxspi->hdmarx->XferAbortCallback = NULL; in HAL_XSPI_Receive_DMA()
1710 if ((hxspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) in HAL_XSPI_Receive_DMA()
1712 if (hxspi->hdmarx->LinkedListQueue != NULL) in HAL_XSPI_Receive_DMA()
1720 p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hxspi->XferSize; in HAL_XSPI_Receive_DMA()
1722 p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hxspi->Instance->DR; in HAL_XSPI_Receive_DMA()
1726 status = HAL_DMAEx_List_Start_IT(hxspi->hdmarx); in HAL_XSPI_Receive_DMA()
1731 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Receive_DMA()
1733 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Receive_DMA()
1741 …if ((hxspi->hdmarx->Init.Direction == DMA_PERIPH_TO_MEMORY) && (hxspi->hdmarx->Init.SrcInc == DMA_… in HAL_XSPI_Receive_DMA()
1742 && (hxspi->hdmarx->Init.DestInc == DMA_DINC_INCREMENTED)) in HAL_XSPI_Receive_DMA()
1744 …status = HAL_DMA_Start_IT(hxspi->hdmarx, (uint32_t)&hxspi->Instance->DR, (uint32_t)pData, hxspi->X… in HAL_XSPI_Receive_DMA()
1749 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_Receive_DMA()
1756 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TE); in HAL_XSPI_Receive_DMA()
1759 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_Receive_DMA()
1761 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_DMA()
1765 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_Receive_DMA()
1767 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_Receive_DMA()
1771 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_Receive_DMA()
1776 SET_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Receive_DMA()
1781 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Receive_DMA()
1782 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Receive_DMA()
1789 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Receive_DMA()
1804 HAL_StatusTypeDef HAL_XSPI_AutoPolling(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const pC… in HAL_XSPI_AutoPolling() argument
1809 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_AutoPolling()
1810 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_AutoPolling()
1812 uint32_t dlr_reg = hxspi->Instance->DLR; in HAL_XSPI_AutoPolling()
1822 …if ((hxspi->State == HAL_XSPI_STATE_CMD_CFG) && (pCfg->AutomaticStop == HAL_XSPI_AUTOMATIC_STOP_EN… in HAL_XSPI_AutoPolling()
1825 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_XSPI_AutoPolling()
1830 WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); in HAL_XSPI_AutoPolling()
1831 WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); in HAL_XSPI_AutoPolling()
1832 WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); in HAL_XSPI_AutoPolling()
1833 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), in HAL_XSPI_AutoPolling()
1837 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_AutoPolling()
1839 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling()
1843 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_AutoPolling()
1845 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling()
1849 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_AutoPolling()
1854 status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_SM, SET, tickstart, Timeout); in HAL_XSPI_AutoPolling()
1859 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_SM); in HAL_XSPI_AutoPolling()
1861 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_AutoPolling()
1872 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_AutoPolling()
1885 HAL_StatusTypeDef HAL_XSPI_AutoPolling_IT(XSPI_HandleTypeDef *hxspi, XSPI_AutoPollingTypeDef *const… in HAL_XSPI_AutoPolling_IT() argument
1889 uint32_t addr_reg = hxspi->Instance->AR; in HAL_XSPI_AutoPolling_IT()
1890 uint32_t ir_reg = hxspi->Instance->IR; in HAL_XSPI_AutoPolling_IT()
1892 uint32_t dlr_reg = hxspi->Instance->DLR; in HAL_XSPI_AutoPolling_IT()
1902 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_AutoPolling_IT()
1905 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_AutoPolling_IT()
1910 WRITE_REG(hxspi->Instance->PSMAR, pCfg->MatchValue); in HAL_XSPI_AutoPolling_IT()
1911 WRITE_REG(hxspi->Instance->PSMKR, pCfg->MatchMask); in HAL_XSPI_AutoPolling_IT()
1912 WRITE_REG(hxspi->Instance->PIR, pCfg->IntervalTime); in HAL_XSPI_AutoPolling_IT()
1913 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_PMM | XSPI_CR_APMS | XSPI_CR_FMODE), in HAL_XSPI_AutoPolling_IT()
1917 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TE | HAL_XSPI_FLAG_SM); in HAL_XSPI_AutoPolling_IT()
1919 hxspi->State = HAL_XSPI_STATE_BUSY_AUTO_POLLING; in HAL_XSPI_AutoPolling_IT()
1922 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_SM | HAL_XSPI_IT_TE); in HAL_XSPI_AutoPolling_IT()
1925 if (hxspi->Init.MemoryType == HAL_XSPI_MEMTYPE_HYPERBUS) in HAL_XSPI_AutoPolling_IT()
1927 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling_IT()
1931 if (READ_BIT(hxspi->Instance->CCR, XSPI_CCR_ADMODE) != HAL_XSPI_ADDRESS_NONE) in HAL_XSPI_AutoPolling_IT()
1933 WRITE_REG(hxspi->Instance->AR, addr_reg); in HAL_XSPI_AutoPolling_IT()
1937 WRITE_REG(hxspi->Instance->IR, ir_reg); in HAL_XSPI_AutoPolling_IT()
1945 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_AutoPolling_IT()
1958 HAL_StatusTypeDef HAL_XSPI_MemoryMapped(XSPI_HandleTypeDef *hxspi, XSPI_MemoryMappedTypeDef *const … in HAL_XSPI_MemoryMapped() argument
1967 if (hxspi->State == HAL_XSPI_STATE_CMD_CFG) in HAL_XSPI_MemoryMapped()
1970 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_MemoryMapped()
1974 hxspi->State = HAL_XSPI_STATE_BUSY_MEM_MAPPED; in HAL_XSPI_MemoryMapped()
1981 WRITE_REG(hxspi->Instance->LPTR, pCfg->TimeoutPeriodClock); in HAL_XSPI_MemoryMapped()
1984 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TO); in HAL_XSPI_MemoryMapped()
1987 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TO); in HAL_XSPI_MemoryMapped()
1991 MODIFY_REG(hxspi->Instance->CR, (XSPI_CR_TCEN | XSPI_CR_FMODE), in HAL_XSPI_MemoryMapped()
1998 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_MemoryMapped()
2009 __weak void HAL_XSPI_ErrorCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_ErrorCallback() argument
2012 UNUSED(hxspi); in HAL_XSPI_ErrorCallback()
2024 __weak void HAL_XSPI_AbortCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_AbortCpltCallback() argument
2027 UNUSED(hxspi); in HAL_XSPI_AbortCpltCallback()
2039 __weak void HAL_XSPI_FifoThresholdCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_FifoThresholdCallback() argument
2042 UNUSED(hxspi); in HAL_XSPI_FifoThresholdCallback()
2054 __weak void HAL_XSPI_CmdCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_CmdCpltCallback() argument
2057 UNUSED(hxspi); in HAL_XSPI_CmdCpltCallback()
2069 __weak void HAL_XSPI_RxCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_RxCpltCallback() argument
2072 UNUSED(hxspi); in HAL_XSPI_RxCpltCallback()
2084 __weak void HAL_XSPI_TxCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_TxCpltCallback() argument
2087 UNUSED(hxspi); in HAL_XSPI_TxCpltCallback()
2099 __weak void HAL_XSPI_RxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_RxHalfCpltCallback() argument
2102 UNUSED(hxspi); in HAL_XSPI_RxHalfCpltCallback()
2114 __weak void HAL_XSPI_TxHalfCpltCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_TxHalfCpltCallback() argument
2117 UNUSED(hxspi); in HAL_XSPI_TxHalfCpltCallback()
2129 __weak void HAL_XSPI_StatusMatchCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_StatusMatchCallback() argument
2132 UNUSED(hxspi); in HAL_XSPI_StatusMatchCallback()
2144 __weak void HAL_XSPI_TimeOutCallback(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_TimeOutCallback() argument
2147 UNUSED(hxspi); in HAL_XSPI_TimeOutCallback()
2176 HAL_StatusTypeDef HAL_XSPI_RegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef C… in HAL_XSPI_RegisterCallback() argument
2184 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2188 if (hxspi->State == HAL_XSPI_STATE_READY) in HAL_XSPI_RegisterCallback()
2193 hxspi->ErrorCallback = pCallback; in HAL_XSPI_RegisterCallback()
2196 hxspi->AbortCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2199 hxspi->FifoThresholdCallback = pCallback; in HAL_XSPI_RegisterCallback()
2202 hxspi->CmdCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2205 hxspi->RxCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2208 hxspi->TxCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2211 hxspi->RxHalfCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2214 hxspi->TxHalfCpltCallback = pCallback; in HAL_XSPI_RegisterCallback()
2217 hxspi->StatusMatchCallback = pCallback; in HAL_XSPI_RegisterCallback()
2220 hxspi->TimeOutCallback = pCallback; in HAL_XSPI_RegisterCallback()
2223 hxspi->MspInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2226 hxspi->MspDeInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2230 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2236 else if (hxspi->State == HAL_XSPI_STATE_RESET) in HAL_XSPI_RegisterCallback()
2241 hxspi->MspInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2244 hxspi->MspDeInitCallback = pCallback; in HAL_XSPI_RegisterCallback()
2248 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2257 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_RegisterCallback()
2285 HAL_StatusTypeDef HAL_XSPI_UnRegisterCallback(XSPI_HandleTypeDef *hxspi, HAL_XSPI_CallbackIDTypeDef… in HAL_XSPI_UnRegisterCallback() argument
2289 if (hxspi->State == HAL_XSPI_STATE_READY) in HAL_XSPI_UnRegisterCallback()
2294 hxspi->ErrorCallback = HAL_XSPI_ErrorCallback; in HAL_XSPI_UnRegisterCallback()
2297 hxspi->AbortCpltCallback = HAL_XSPI_AbortCpltCallback; in HAL_XSPI_UnRegisterCallback()
2300 hxspi->FifoThresholdCallback = HAL_XSPI_FifoThresholdCallback; in HAL_XSPI_UnRegisterCallback()
2303 hxspi->CmdCpltCallback = HAL_XSPI_CmdCpltCallback; in HAL_XSPI_UnRegisterCallback()
2306 hxspi->RxCpltCallback = HAL_XSPI_RxCpltCallback; in HAL_XSPI_UnRegisterCallback()
2309 hxspi->TxCpltCallback = HAL_XSPI_TxCpltCallback; in HAL_XSPI_UnRegisterCallback()
2312 hxspi->RxHalfCpltCallback = HAL_XSPI_RxHalfCpltCallback; in HAL_XSPI_UnRegisterCallback()
2315 hxspi->TxHalfCpltCallback = HAL_XSPI_TxHalfCpltCallback; in HAL_XSPI_UnRegisterCallback()
2318 hxspi->StatusMatchCallback = HAL_XSPI_StatusMatchCallback; in HAL_XSPI_UnRegisterCallback()
2321 hxspi->TimeOutCallback = HAL_XSPI_TimeOutCallback; in HAL_XSPI_UnRegisterCallback()
2324 hxspi->MspInitCallback = HAL_XSPI_MspInit; in HAL_XSPI_UnRegisterCallback()
2327 hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; in HAL_XSPI_UnRegisterCallback()
2331 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_UnRegisterCallback()
2337 else if (hxspi->State == HAL_XSPI_STATE_RESET) in HAL_XSPI_UnRegisterCallback()
2342 hxspi->MspInitCallback = HAL_XSPI_MspInit; in HAL_XSPI_UnRegisterCallback()
2345 hxspi->MspDeInitCallback = HAL_XSPI_MspDeInit; in HAL_XSPI_UnRegisterCallback()
2349 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_UnRegisterCallback()
2358 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_CALLBACK; in HAL_XSPI_UnRegisterCallback()
2395 HAL_StatusTypeDef HAL_XSPI_Abort(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_Abort() argument
2401 if (hxspi->State != HAL_XSPI_STATE_RESET) in HAL_XSPI_Abort()
2404 if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) in HAL_XSPI_Abort()
2407 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Abort()
2410 status = HAL_DMA_Abort(hxspi->hdmatx); in HAL_XSPI_Abort()
2413 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Abort()
2417 status = HAL_DMA_Abort(hxspi->hdmarx); in HAL_XSPI_Abort()
2420 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in HAL_XSPI_Abort()
2424 if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) in HAL_XSPI_Abort()
2427 SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); in HAL_XSPI_Abort()
2430 … status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_TC, SET, tickstart, hxspi->Timeout); in HAL_XSPI_Abort()
2435 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Abort()
2438 …status = XSPI_WaitFlagStateUntilTimeout(hxspi, HAL_XSPI_FLAG_BUSY, RESET, tickstart, hxspi->Timeou… in HAL_XSPI_Abort()
2443 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort()
2445 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort()
2452 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort()
2454 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort()
2460 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Abort()
2471 HAL_StatusTypeDef HAL_XSPI_Abort_IT(XSPI_HandleTypeDef *hxspi) in HAL_XSPI_Abort_IT() argument
2476 if (hxspi->State != HAL_XSPI_STATE_RESET) in HAL_XSPI_Abort_IT()
2479 …HAL_XSPI_DISABLE_IT(hxspi, (HAL_XSPI_IT_TO | HAL_XSPI_IT_SM | HAL_XSPI_IT_FT | HAL_XSPI_IT_TC | HA… in HAL_XSPI_Abort_IT()
2481 hxspi->State = HAL_XSPI_STATE_ABORT; in HAL_XSPI_Abort_IT()
2484 if ((hxspi->Instance->CR & XSPI_CR_DMAEN) != 0U) in HAL_XSPI_Abort_IT()
2487 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in HAL_XSPI_Abort_IT()
2490 hxspi->hdmatx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_Abort_IT()
2491 if (HAL_DMA_Abort_IT(hxspi->hdmatx) != HAL_OK) in HAL_XSPI_Abort_IT()
2493 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort_IT()
2497 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2499 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2504 hxspi->hdmarx->XferAbortCallback = XSPI_DMAAbortCplt; in HAL_XSPI_Abort_IT()
2505 if (HAL_DMA_Abort_IT(hxspi->hdmarx) != HAL_OK) in HAL_XSPI_Abort_IT()
2507 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort_IT()
2511 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2513 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2519 if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) in HAL_XSPI_Abort_IT()
2522 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in HAL_XSPI_Abort_IT()
2525 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); in HAL_XSPI_Abort_IT()
2528 SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); in HAL_XSPI_Abort_IT()
2531 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort_IT()
2536 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_FMODE); in HAL_XSPI_Abort_IT()
2538 hxspi->State = HAL_XSPI_STATE_READY; in HAL_XSPI_Abort_IT()
2542 hxspi->AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2544 HAL_XSPI_AbortCpltCallback(hxspi); in HAL_XSPI_Abort_IT()
2552 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_Abort_IT()
2563 HAL_StatusTypeDef HAL_XSPI_SetFifoThreshold(XSPI_HandleTypeDef *hxspi, uint32_t Threshold) in HAL_XSPI_SetFifoThreshold() argument
2570 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetFifoThreshold()
2573 hxspi->Init.FifoThresholdByte = Threshold; in HAL_XSPI_SetFifoThreshold()
2576 …MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FTHRES, ((hxspi->Init.FifoThresholdByte - 1U) << XSPI_CR_F… in HAL_XSPI_SetFifoThreshold()
2582 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetFifoThreshold()
2592 uint32_t HAL_XSPI_GetFifoThreshold(const XSPI_HandleTypeDef *hxspi) in HAL_XSPI_GetFifoThreshold() argument
2594 return ((READ_BIT(hxspi->Instance->CR, XSPI_CR_FTHRES) >> XSPI_CR_FTHRES_Pos) + 1U); in HAL_XSPI_GetFifoThreshold()
2602 HAL_StatusTypeDef HAL_XSPI_SetMemoryType(XSPI_HandleTypeDef *hxspi, uint32_t Type) in HAL_XSPI_SetMemoryType() argument
2609 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetMemoryType()
2612 hxspi->Init.MemoryType = Type; in HAL_XSPI_SetMemoryType()
2615 MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_MTYP, hxspi->Init.MemoryType); in HAL_XSPI_SetMemoryType()
2620 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetMemoryType()
2631 HAL_StatusTypeDef HAL_XSPI_SetDeviceSize(XSPI_HandleTypeDef *hxspi, uint32_t Size) in HAL_XSPI_SetDeviceSize() argument
2638 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetDeviceSize()
2641 hxspi->Init.MemorySize = Size; in HAL_XSPI_SetDeviceSize()
2644 MODIFY_REG(hxspi->Instance->DCR1, XSPI_DCR1_DEVSIZE, in HAL_XSPI_SetDeviceSize()
2645 (hxspi->Init.MemorySize << XSPI_DCR1_DEVSIZE_Pos)); in HAL_XSPI_SetDeviceSize()
2650 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetDeviceSize()
2661 HAL_StatusTypeDef HAL_XSPI_SetClockPrescaler(XSPI_HandleTypeDef *hxspi, uint32_t Prescaler) in HAL_XSPI_SetClockPrescaler() argument
2667 if ((hxspi->State & XSPI_BUSY_STATE_MASK) == 0U) in HAL_XSPI_SetClockPrescaler()
2670 hxspi->Init.ClockPrescaler = Prescaler; in HAL_XSPI_SetClockPrescaler()
2673 MODIFY_REG(hxspi->Instance->DCR2, XSPI_DCR2_PRESCALER, in HAL_XSPI_SetClockPrescaler()
2674 ((hxspi->Init.ClockPrescaler) << XSPI_DCR2_PRESCALER_Pos)); in HAL_XSPI_SetClockPrescaler()
2679 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_SEQUENCE; in HAL_XSPI_SetClockPrescaler()
2690 HAL_StatusTypeDef HAL_XSPI_SetTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Timeout) in HAL_XSPI_SetTimeout() argument
2692 hxspi->Timeout = Timeout; in HAL_XSPI_SetTimeout()
2701 uint32_t HAL_XSPI_GetError(const XSPI_HandleTypeDef *hxspi) in HAL_XSPI_GetError() argument
2703 return hxspi->ErrorCode; in HAL_XSPI_GetError()
2711 uint32_t HAL_XSPI_GetState(const XSPI_HandleTypeDef *hxspi) in HAL_XSPI_GetState() argument
2714 return hxspi->State; in HAL_XSPI_GetState()
2742 HAL_StatusTypeDef HAL_XSPI_DLYB_SetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *con… in HAL_XSPI_DLYB_SetConfig() argument
2747 SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DLYB_SetConfig()
2750 hxspi->State = HAL_XSPI_STATE_BUSY_CMD; in HAL_XSPI_DLYB_SetConfig()
2752 if (hxspi->Instance == OCTOSPI1) in HAL_XSPI_DLYB_SetConfig()
2763 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_DLYB_SetConfig()
2767 (void)HAL_XSPI_Abort(hxspi); in HAL_XSPI_DLYB_SetConfig()
2770 CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DLYB_SetConfig()
2781 HAL_StatusTypeDef HAL_XSPI_DLYB_GetConfig(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef *con… in HAL_XSPI_DLYB_GetConfig() argument
2785 if (hxspi->Instance == OCTOSPI1) in HAL_XSPI_DLYB_GetConfig()
2792 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_DLYB_GetConfig()
2804 HAL_StatusTypeDef HAL_XSPI_DLYB_GetClockPeriod(XSPI_HandleTypeDef *hxspi, HAL_XSPI_DLYB_CfgTypeDef … in HAL_XSPI_DLYB_GetClockPeriod() argument
2809 SET_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DLYB_GetClockPeriod()
2812 hxspi->State = HAL_XSPI_STATE_BUSY_CMD; in HAL_XSPI_DLYB_GetClockPeriod()
2814 if (hxspi->Instance == OCTOSPI1) in HAL_XSPI_DLYB_GetClockPeriod()
2830 hxspi->ErrorCode |= HAL_XSPI_ERROR_INVALID_PARAM; in HAL_XSPI_DLYB_GetClockPeriod()
2834 (void)HAL_XSPI_Abort(hxspi); in HAL_XSPI_DLYB_GetClockPeriod()
2837 CLEAR_BIT(hxspi->Instance->DCR1, XSPI_DCR1_FRCK); in HAL_XSPI_DLYB_GetClockPeriod()
2852 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMACplt() local
2853 hxspi->XferCount = 0; in XSPI_DMACplt()
2856 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in XSPI_DMACplt()
2859 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); in XSPI_DMACplt()
2869 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMAHalfCplt() local
2870 hxspi->XferCount = (hxspi->XferCount >> 1); in XSPI_DMAHalfCplt()
2872 if (hxspi->State == HAL_XSPI_STATE_BUSY_RX) in XSPI_DMAHalfCplt()
2875 hxspi->RxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
2877 HAL_XSPI_RxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
2883 hxspi->TxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
2885 HAL_XSPI_TxHalfCpltCallback(hxspi); in XSPI_DMAHalfCplt()
2897 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMAError() local
2898 hxspi->XferCount = 0; in XSPI_DMAError()
2899 hxspi->ErrorCode = HAL_XSPI_ERROR_DMA; in XSPI_DMAError()
2902 CLEAR_BIT(hxspi->Instance->CR, XSPI_CR_DMAEN); in XSPI_DMAError()
2905 if (HAL_XSPI_Abort_IT(hxspi) != HAL_OK) in XSPI_DMAError()
2908 HAL_XSPI_DISABLE_IT(hxspi, HAL_XSPI_IT_TC | HAL_XSPI_IT_FT | HAL_XSPI_IT_TE); in XSPI_DMAError()
2910 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_DMAError()
2914 hxspi->ErrorCallback(hxspi); in XSPI_DMAError()
2916 HAL_XSPI_ErrorCallback(hxspi); in XSPI_DMAError()
2928 XSPI_HandleTypeDef *hxspi = (XSPI_HandleTypeDef *)(hdma->Parent); in XSPI_DMAAbortCplt() local
2929 hxspi->XferCount = 0; in XSPI_DMAAbortCplt()
2932 if (hxspi->State == HAL_XSPI_STATE_ABORT) in XSPI_DMAAbortCplt()
2935 if (HAL_XSPI_GET_FLAG(hxspi, HAL_XSPI_FLAG_BUSY) != RESET) in XSPI_DMAAbortCplt()
2938 HAL_XSPI_CLEAR_FLAG(hxspi, HAL_XSPI_FLAG_TC); in XSPI_DMAAbortCplt()
2941 HAL_XSPI_ENABLE_IT(hxspi, HAL_XSPI_IT_TC); in XSPI_DMAAbortCplt()
2944 SET_BIT(hxspi->Instance->CR, XSPI_CR_ABORT); in XSPI_DMAAbortCplt()
2948 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_DMAAbortCplt()
2952 hxspi->AbortCpltCallback(hxspi); in XSPI_DMAAbortCplt()
2954 HAL_XSPI_AbortCpltCallback(hxspi); in XSPI_DMAAbortCplt()
2961 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_DMAAbortCplt()
2965 hxspi->ErrorCallback(hxspi); in XSPI_DMAAbortCplt()
2967 HAL_XSPI_ErrorCallback(hxspi); in XSPI_DMAAbortCplt()
2981 static HAL_StatusTypeDef XSPI_WaitFlagStateUntilTimeout(XSPI_HandleTypeDef *hxspi, uint32_t Flag, in XSPI_WaitFlagStateUntilTimeout() argument
2985 while ((HAL_XSPI_GET_FLAG(hxspi, Flag)) != State) in XSPI_WaitFlagStateUntilTimeout()
2992 hxspi->State = HAL_XSPI_STATE_READY; in XSPI_WaitFlagStateUntilTimeout()
2993 hxspi->ErrorCode |= HAL_XSPI_ERROR_TIMEOUT; in XSPI_WaitFlagStateUntilTimeout()
3008 static HAL_StatusTypeDef XSPI_ConfigCmd(XSPI_HandleTypeDef *hxspi, XSPI_RegularCmdTypeDef *pCmd) in XSPI_ConfigCmd() argument
3017 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_FMODE, 0U); in XSPI_ConfigCmd()
3019 if (hxspi->Init.MemoryMode == HAL_XSPI_SINGLE_MEM) in XSPI_ConfigCmd()
3022 MODIFY_REG(hxspi->Instance->CR, XSPI_CR_MSEL, pCmd->IOSelect); in XSPI_ConfigCmd()
3027 ccr_reg = &(hxspi->Instance->WCCR); in XSPI_ConfigCmd()
3028 tcr_reg = &(hxspi->Instance->WTCR); in XSPI_ConfigCmd()
3029 ir_reg = &(hxspi->Instance->WIR); in XSPI_ConfigCmd()
3030 abr_reg = &(hxspi->Instance->WABR); in XSPI_ConfigCmd()
3034 ccr_reg = &(hxspi->Instance->WPCCR); in XSPI_ConfigCmd()
3035 tcr_reg = &(hxspi->Instance->WPTCR); in XSPI_ConfigCmd()
3036 ir_reg = &(hxspi->Instance->WPIR); in XSPI_ConfigCmd()
3037 abr_reg = &(hxspi->Instance->WPABR); in XSPI_ConfigCmd()
3041 ccr_reg = &(hxspi->Instance->CCR); in XSPI_ConfigCmd()
3042 tcr_reg = &(hxspi->Instance->TCR); in XSPI_ConfigCmd()
3043 ir_reg = &(hxspi->Instance->IR); in XSPI_ConfigCmd()
3044 abr_reg = &(hxspi->Instance->ABR); in XSPI_ConfigCmd()
3076 hxspi->Instance->DLR = (pCmd->DataLength - 1U); in XSPI_ConfigCmd()
3086 CLEAR_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); in XSPI_ConfigCmd()
3088 else if (hxspi->Init.SampleShifting == HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE) in XSPI_ConfigCmd()
3091 SET_BIT(hxspi->Instance->TCR, XSPI_TCR_SSHIFT); in XSPI_ConfigCmd()
3126 if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && in XSPI_ConfigCmd()
3136 hxspi->Instance->AR = pCmd->Address; in XSPI_ConfigCmd()
3159 if ((hxspi->Init.DelayHoldQuarterCycle == HAL_XSPI_DHQC_ENABLE) && in XSPI_ConfigCmd()
3195 hxspi->Instance->AR = pCmd->Address; in XSPI_ConfigCmd()
3201 hxspi->ErrorCode = HAL_XSPI_ERROR_INVALID_PARAM; in XSPI_ConfigCmd()