92 #if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED)
179   if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_ConfigAssociativityMode()
185     MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode);  in HAL_ICACHE_ConfigAssociativityMode()
198   WRITE_REG(ICACHE->IER, 0U);  in HAL_ICACHE_DeInit()
201   WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF);  in HAL_ICACHE_DeInit()
204   CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);  in HAL_ICACHE_DeInit()
205   WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL);  in HAL_ICACHE_DeInit()
208   CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS);  in HAL_ICACHE_DeInit()
209   SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));  in HAL_ICACHE_DeInit()
210   CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U));  in HAL_ICACHE_DeInit()
214   WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);  in HAL_ICACHE_DeInit()
215   WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);  in HAL_ICACHE_DeInit()
216   WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);  in HAL_ICACHE_DeInit()
217   WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos);  in HAL_ICACHE_DeInit()
232   SET_BIT(ICACHE->CR, ICACHE_CR_EN);  in HAL_ICACHE_Enable()
250   WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);  in HAL_ICACHE_Disable()
252   CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN);  in HAL_ICACHE_Disable()
258   while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_Disable()
263       if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_Disable()
280   return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL);  in HAL_ICACHE_IsEnabled()
294   if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U)  in HAL_ICACHE_Invalidate()
297     SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);  in HAL_ICACHE_Invalidate()
318   if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)  in HAL_ICACHE_Invalidate_IT()
325     WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);  in HAL_ICACHE_Invalidate_IT()
328     SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);  in HAL_ICACHE_Invalidate_IT()
331     SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV);  in HAL_ICACHE_Invalidate_IT()
348   if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U)  in HAL_ICACHE_WaitForInvalidateComplete()
354     while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)  in HAL_ICACHE_WaitForInvalidateComplete()
359         if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U)  in HAL_ICACHE_WaitForInvalidateComplete()
369   WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);  in HAL_ICACHE_WaitForInvalidateComplete()
389   SET_BIT(ICACHE->CR, MonitorType);  in HAL_ICACHE_Monitor_Start()
409   CLEAR_BIT(ICACHE->CR, MonitorType);  in HAL_ICACHE_Monitor_Stop()
429   SET_BIT(ICACHE->CR, (MonitorType << 2U));  in HAL_ICACHE_Monitor_Reset()
430   CLEAR_BIT(ICACHE->CR, (MonitorType << 2U));  in HAL_ICACHE_Monitor_Reset()
442   return (ICACHE->HMONR);  in HAL_ICACHE_Monitor_GetHitValue()
452   return (ICACHE->MMONR);  in HAL_ICACHE_Monitor_GetMissValue()
483   uint32_t itflags   = READ_REG(ICACHE->SR);  in HAL_ICACHE_IRQHandler()
484   uint32_t itsources = READ_REG(ICACHE->IER);  in HAL_ICACHE_IRQHandler()
490     CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE);  in HAL_ICACHE_IRQHandler()
493     WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF);  in HAL_ICACHE_IRQHandler()
503     CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE);  in HAL_ICACHE_IRQHandler()
506     WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF);  in HAL_ICACHE_IRQHandler()
573   if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_EnableRemapRegion()
580     p_reg = &(ICACHE->CRR0) + (1U * Region);  in HAL_ICACHE_EnableRemapRegion()
624   if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U)  in HAL_ICACHE_DisableRemapRegion()
631     p_reg = &(ICACHE->CRR0) + (1U * Region);  in HAL_ICACHE_DisableRemapRegion()