Lines Matching refs:SBS
714 MODIFY_REG(SBS->PMCR, SBS_PMCR_ETH_SEL_PHY, (uint32_t)(SBS_ETHInterface)); in HAL_SBS_ETHInterfaceSelect()
726 SET_BIT(SBS->CCCSR, SBS_CCCSR_EN1) ; in HAL_SBS_EnableVddIO1CompensationCell()
737 CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN1); in HAL_SBS_DisableVddIO1CompensationCell()
748 SET_BIT(SBS->CCCSR, SBS_CCCSR_EN2) ; in HAL_SBS_EnableVddIO2CompensationCell()
759 CLEAR_BIT(SBS->CCCSR, SBS_CCCSR_EN2); in HAL_SBS_DisableVddIO2CompensationCell()
774 MODIFY_REG(SBS->CCCSR, SBS_CCCSR_CS1, (uint32_t)(SBS_CompCode)); in HAL_SBS_VDDCompensationCodeSelect()
789 MODIFY_REG(SBS->CCCSR, SBS_CCCSR_CS2, (uint32_t)(SBS_CompCode)); in HAL_SBS_VDDIOCompensationCodeSelect()
798 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY1) == SBS_CCCSR_RDY1) ? 1UL : 0UL); in HAL_SBS_GetVddIO1CompensationCellReadyFlag()
807 return ((READ_BIT(SBS->CCCSR, SBS_CCCSR_RDY2) == SBS_CCCSR_RDY2) ? 1UL : 0UL); in HAL_SBS_GetVddIO2CompensationCellReadyFlag()
825 …MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC1 | SBS_CCSWCR_SW_APSRC1, (((uint32_t)(SBS_PMOSCode) <<… in HAL_SBS_VDDCompensationCodeConfig()
844 …MODIFY_REG(SBS->CCSWCR, SBS_CCSWCR_SW_ANSRC2 | SBS_CCSWCR_SW_APSRC2, (((uint32_t)(SBS_PMOSCode) <<… in HAL_SBS_VDDIOCompensationCodeConfig()
854 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC1)); in HAL_SBS_GetNMOSVddCompensationValue()
863 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC1) >> SBS_CCVALR_APSRC1_Pos); in HAL_SBS_GetPMOSVddCompensationValue()
872 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_ANSRC2) >> SBS_CCVALR_ANSRC2_Pos); in HAL_SBS_GetNMOSVddIO2CompensationValue()
882 return (uint32_t)(READ_BIT(SBS->CCVALR, SBS_CCVALR_APSRC2) >> SBS_CCVALR_APSRC2_Pos); in HAL_SBS_GetPMOSVddIO2CompensationValue()
892 SET_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); in HAL_SBS_FLASH_DisableECCNMI()
902 CLEAR_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN); in HAL_SBS_FLASH_EnableECCNMI()
912 …return ((READ_BIT(SBS->ECCNMIR, SBS_ECCNMIR_ECCNMI_MASK_EN) == SBS_ECCNMIR_ECCNMI_MASK_EN) ? 1UL :… in HAL_SBS_FLASH_ECCNMI_IsDisabled()
940 MODIFY_REG(SBS->HDPLCR, SBS_HDPLCR_INCR_HDPL, SBS_HDPL_INCREMENT_VALUE); in HAL_SBS_IncrementHDPLValue()
955 return (uint32_t)(READ_BIT(SBS->HDPLSR, SBS_HDPLSR_HDPL)); in HAL_SBS_GetHDPLValue()
993 MODIFY_REG(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL, (uint32_t)(Epoch_Selection)); in HAL_SBS_EPOCHSelection()
1005 return (uint32_t)(READ_BIT(SBS->EPOCHSELCR, SBS_EPOCHSELCR_EPOCH_SEL)); in HAL_SBS_GetEPOCHSelection()
1025 MODIFY_REG(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL, (uint32_t)(OBKHDPL_Value)); in HAL_SBS_SetOBKHDPL()
1039 return (uint32_t)(READ_BIT(SBS->NEXTHDPLCR, SBS_NEXTHDPLCR_NEXTHDPL)); in HAL_SBS_GetOBKHDPL()
1073 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_AP_UNLOCK, SBS_DEBUG_UNLOCK_VALUE); in HAL_SBS_OpenAccessPort()
1083 …MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_UNLOCK, (SBS_DEBUG_UNLOCK_VALUE << SBS_DBGCR_DBG_UNLOCK_Pos)); in HAL_SBS_OpenDebug()
1101 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_HDPL, (Level << SBS_DBGCR_DBG_AUTH_HDPL_Pos)); in HAL_SBS_ConfigDebugLevel()
1118 return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_HDPL) >> SBS_DBGCR_DBG_AUTH_HDPL_Pos); in HAL_SBS_GetDebugLevel()
1129 MODIFY_REG(SBS->DBGLOCKR, SBS_DBGLOCKR_DBGCFG_LOCK, SBS_DEBUG_LOCK_VALUE); in HAL_SBS_LockDebugConfig()
1143 MODIFY_REG(SBS->DBGCR, SBS_DBGCR_DBG_AUTH_SEC, (Security << SBS_DBGCR_DBG_AUTH_SEC_Pos)); in HAL_SBS_ConfigDebugSecurity()
1155 return ((SBS->DBGCR & SBS_DBGCR_DBG_AUTH_SEC) >> SBS_DBGCR_DBG_AUTH_SEC_Pos); in HAL_SBS_GetDebugSecurity()
1189 SBS->CNSLCKR = (0xFFFFU & Item); /* non-secure lock item in 16 lowest bits */ in HAL_SBS_Lock()
1193 SBS->CSLCKR = ((0xFFFF0000U & Item) >> 16U); /* Secure-only lock item in 16 highest bits */ in HAL_SBS_Lock()
1215 tmp_lock = SBS->CNSLCKR; in HAL_SBS_GetLock()
1219 tmp_lock |= (SBS->CSLCKR << 16U); in HAL_SBS_GetLock()
1263 tmp = SBS->SECCFGR; in HAL_SBS_ConfigAttributes()
1276 SBS->SECCFGR = tmp; in HAL_SBS_ConfigAttributes()
1300 if ((SBS->SECCFGR & Item) != 0U) in HAL_SBS_GetConfigAttributes()