Lines Matching refs:PWR
34 #if defined (PWR)
273 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
280 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
309 MODIFY_REG(PWR->PMCR, PWR_PMCR_LPMS, Mode); in LL_PWR_SetPowerMode()
321 return (READ_BIT(PWR->PMCR, PWR_PMCR_LPMS)); in LL_PWR_GetPowerMode()
335 MODIFY_REG(PWR->PMCR, PWR_PMCR_SVOS, VoltageScaling); in LL_PWR_SetStopModeRegulVoltageScaling()
348 return (uint32_t)(READ_BIT(PWR->PMCR, PWR_PMCR_SVOS)); in LL_PWR_GetStopModeRegulVoltageScaling()
358 SET_BIT(PWR->PMCR, PWR_PMCR_FLPS); in LL_PWR_EnableFlashPowerDown()
368 CLEAR_BIT(PWR->PMCR, PWR_PMCR_FLPS); in LL_PWR_DisableFlashPowerDown()
378 return ((READ_BIT(PWR->PMCR, PWR_PMCR_FLPS) == (PWR_PMCR_FLPS)) ? 1UL : 0UL); in LL_PWR_IsEnabledFlashPowerDown()
388 SET_BIT(PWR->PMCR, PWR_PMCR_BOOSTE); in LL_PWR_EnableAnalogBooster()
398 CLEAR_BIT(PWR->PMCR, PWR_PMCR_BOOSTE); in LL_PWR_DisableAnalogBooster()
408 return ((READ_BIT(PWR->PMCR, PWR_PMCR_BOOSTE) == (PWR_PMCR_BOOSTE)) ? 1UL : 0UL); in LL_PWR_IsEnabledAnalogBooster()
418 SET_BIT(PWR->PMCR, PWR_PMCR_AVD_READY); in LL_PWR_EnableAnalogVoltageReady()
428 CLEAR_BIT(PWR->PMCR, PWR_PMCR_AVD_READY); in LL_PWR_DisableAnalogVoltageReady()
438 return ((READ_BIT(PWR->PMCR, PWR_PMCR_AVD_READY) == (PWR_PMCR_AVD_READY)) ? 1UL : 0UL); in LL_PWR_IsEnabledAnalogVoltageReady()
448 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO); in LL_PWR_EnableAHBRAM1ShutOff()
458 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO); in LL_PWR_DisableAHBRAM1ShutOff()
468 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO) == (PWR_PMCR_SRAM1SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAHBRAM1ShutOff()
478 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO); in LL_PWR_EnableAHBRAM2_48K_ShutOff()
488 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO); in LL_PWR_DisableAHBRAM2_48K_ShutOff()
498 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO) == (PWR_PMCR_SRAM2_48SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAHBRAM2_48K_ShutOff()
510 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO); in LL_PWR_EnableAHBRAM2_16K_ShutOff()
520 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO); in LL_PWR_DisableAHBRAM2_16K_ShutOff()
530 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO) == (PWR_PMCR_SRAM2_16SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAHBRAM2_16K_ShutOff()
542 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO); in LL_PWR_EnableAHBRAM2_High_16K_ShutOff()
552 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO); in LL_PWR_DisableAHBRAM2_High_16K_ShutOff()
562 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO) == (PWR_PMCR_SRAM2_16HSO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAHBRAM2_High_16K_ShutOff()
574 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO); in LL_PWR_EnableAHBRAM2_Low_16K_ShutOff()
584 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO); in LL_PWR_DisableAHBRAM2_Low_16K_ShutOff()
594 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO) == (PWR_PMCR_SRAM2_16LSO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAHBRAM2_Low_16K_ShutOff()
606 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO); in LL_PWR_EnableAHBRAM2ShutOff()
616 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO); in LL_PWR_DisableAHBRAM2ShutOff()
626 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO) == (PWR_PMCR_SRAM2SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAHBRAM2ShutOff()
638 SET_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO); in LL_PWR_EnableAHBRAM3ShutOff()
648 CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO); in LL_PWR_DisableAHBRAM3ShutOff()
658 return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO) == (PWR_PMCR_SRAM3SO)) ? 1UL : 0UL); in LL_PWR_IsEnabledAHBRAM3ShutOff()
670 SET_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO); in LL_PWR_EnableETHERNETRAMShutOff()
680 CLEAR_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO); in LL_PWR_DisableETHERNETRAMShutOff()
690 return ((READ_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO) == (PWR_PMCR_ETHERNETSO)) ? 1UL : 0UL); in LL_PWR_IsEnabledETHERNETRAMShutOff()
706 MODIFY_REG(PWR->VOSCR, PWR_VOSCR_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
720 return (uint32_t)(READ_BIT(PWR->VOSCR, PWR_VOSCR_VOS)); in LL_PWR_GetRegulVoltageScaling()
734 return (READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOS)); in LL_PWR_GetCurrentVOS()
749 SET_BIT(PWR->BDCR, PWR_BDCR_BREN); in LL_PWR_EnableBkUpRegulator()
759 CLEAR_BIT(PWR->BDCR, PWR_BDCR_BREN); in LL_PWR_DisableBkUpRegulator()
769 return ((READ_BIT(PWR->BDCR, PWR_BDCR_BREN) == (PWR_BDCR_BREN)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpRegulator()
779 SET_BIT(PWR->BDCR, PWR_BDCR_MONEN); in LL_PWR_EnableMonitoring()
789 CLEAR_BIT(PWR->BDCR, PWR_BDCR_MONEN); in LL_PWR_DisableMonitoring()
799 return ((READ_BIT(PWR->BDCR, PWR_BDCR_MONEN) == (PWR_BDCR_MONEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledMonitoring()
809 SET_BIT(PWR->BDCR, PWR_BDCR_VBE); in LL_PWR_EnableBatteryCharging()
819 CLEAR_BIT(PWR->BDCR, PWR_BDCR_VBE); in LL_PWR_DisableBatteryCharging()
829 return ((READ_BIT(PWR->BDCR, PWR_BDCR_VBE) == (PWR_BDCR_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
842 MODIFY_REG(PWR->BDCR, PWR_BDCR_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
854 return (uint32_t)(READ_BIT(PWR->BDCR, PWR_BDCR_VBRS)); in LL_PWR_GetBattChargResistor()
864 SET_BIT(PWR->DBPCR, PWR_DBPCR_DBP); in LL_PWR_EnableBkUpAccess()
874 CLEAR_BIT(PWR->DBPCR, PWR_DBPCR_DBP); in LL_PWR_DisableBkUpAccess()
884 return ((READ_BIT(PWR->DBPCR, PWR_DBPCR_DBP) == (PWR_DBPCR_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
897 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); in LL_PWR_EnableUCPDStandbyMode()
910 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY); in LL_PWR_DisableUCPDStandbyMode()
921 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STBY) == (PWR_UCPDR_UCPD_STBY)) ? 1UL : 0UL); in LL_PWR_IsEnabledUCPDStandbyMode()
938 CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); in LL_PWR_EnableUCPDDeadBattery()
953 SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); in LL_PWR_DisableUCPDDeadBattery()
968 return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL); in LL_PWR_IsEnabledUCPDDeadBattery()
982 MODIFY_REG(PWR->SCCR, (PWR_SCCR_BYPASS), SupplySource); in LL_PWR_ConfigSupply()
994 return (uint32_t)(READ_BIT(PWR->SCCR, (PWR_SCCR_SMPSEN | PWR_SCCR_LDOEN | PWR_SCCR_BYPASS))); in LL_PWR_GetSupply()
997 return (uint32_t)(READ_BIT(PWR->SCCR, (PWR_SCCR_LDOEN | PWR_SCCR_BYPASS))); in LL_PWR_GetSupply()
1008 SET_BIT(PWR->VMCR, PWR_VMCR_PVDEN); in LL_PWR_EnablePVD()
1018 CLEAR_BIT(PWR->VMCR, PWR_VMCR_PVDEN); in LL_PWR_DisablePVD()
1028 return ((READ_BIT(PWR->VMCR, PWR_VMCR_PVDEN) == (PWR_VMCR_PVDEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
1047 MODIFY_REG(PWR->VMCR, PWR_VMCR_PLS, PVDLevel); in LL_PWR_SetPVDLevel()
1065 return (uint32_t)(READ_BIT(PWR->VMCR, PWR_VMCR_PLS)); in LL_PWR_GetPVDLevel()
1076 SET_BIT(PWR->VMCR, PWR_VMCR_AVDEN); in LL_PWR_EnableAVD()
1086 CLEAR_BIT(PWR->VMCR, PWR_VMCR_AVDEN); in LL_PWR_DisableAVD()
1096 return ((READ_BIT(PWR->VMCR, PWR_VMCR_AVDEN) == (PWR_VMCR_AVDEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledAVD()
1111 MODIFY_REG(PWR->VMCR, PWR_VMCR_ALS, AVDLevel); in LL_PWR_SetAVDLevel()
1125 return (uint32_t)(READ_BIT(PWR->VMCR, PWR_VMCR_ALS)); in LL_PWR_GetAVDLevel()
1136 SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN); in LL_PWR_EnableUSBVoltageDetector()
1146 CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN); in LL_PWR_DisableUSBVoltageDetector()
1156 return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_USB33DEN) == (PWR_USBSCR_USB33DEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledUSBVoltageDetector()
1166 SET_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV); in LL_PWR_EnableVddUSB()
1177 CLEAR_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV); in LL_PWR_DisableVddUSB()
1188 return ((READ_BIT(PWR->USBSCR, PWR_USBSCR_USB33SV) == (PWR_USBSCR_USB33SV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddUSB()
1209 SET_BIT(PWR->WUCR, WakeUpPin); in LL_PWR_EnableWakeUpPin()
1228 CLEAR_BIT(PWR->WUCR, WakeUpPin); in LL_PWR_DisableWakeUpPin()
1247 return ((READ_BIT(PWR->WUCR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
1273 SET_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos)); in LL_PWR_SetWakeUpPinPolarityLow()
1299 CLEAR_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos)); in LL_PWR_SetWakeUpPinPolarityHigh()
1325 …return ((READ_BIT(PWR->WUCR, (WakeUpPin << PWR_WUCR_WUPP1_Pos)) == (WakeUpPin << PWR_WUCR_WUPP1_Po… in LL_PWR_IsWakeUpPinPolarityLow()
1352 MODIFY_REG(PWR->WUCR, in LL_PWR_SetWakeUpPinPullNone()
1385 MODIFY_REG(PWR->WUCR, in LL_PWR_SetWakeUpPinPullUp()
1417 MODIFY_REG(PWR->WUCR, in LL_PWR_SetWakeUpPinPullDown()
1452 …uint32_t regValue = READ_BIT(PWR->WUCR, (PWR_WUCR_WUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFS… in LL_PWR_GetWakeUpPinPull()
1468 SET_BIT(PWR->IORETR, PWR_IORETR_IORETEN); in LL_PWR_EnableIORetention()
1478 CLEAR_BIT(PWR->IORETR, PWR_IORETR_IORETEN); in LL_PWR_DisableIORetention()
1488 return ((READ_BIT(PWR->IORETR, PWR_IORETR_IORETEN) == (PWR_IORETR_IORETEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledIORetention()
1498 SET_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN); in LL_PWR_EnableJTAGIORetention()
1508 CLEAR_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN); in LL_PWR_DisableJTAGIORetention()
1518 return ((READ_BIT(PWR->IORETR, PWR_IORETR_JTAGIORETEN) == (PWR_IORETR_JTAGIORETEN)) ? 1UL : 0UL); in LL_PWR_IsEnabledJTAGIORetention()
1536 return ((READ_BIT(PWR->VOSSR, PWR_VOSSR_VOSRDY) == (PWR_VOSSR_VOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
1546 return ((READ_BIT(PWR->PMSR, PWR_PMSR_SBF) == (PWR_PMSR_SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
1556 return ((READ_BIT(PWR->PMSR, PWR_PMSR_STOPF) == (PWR_PMSR_STOPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_STOP()
1566 return ((READ_BIT(PWR->VMSR, PWR_VMSR_PVDO) == (PWR_VMSR_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1576 return ((READ_BIT(PWR->VMSR, PWR_VMSR_AVDO) == (PWR_VMSR_AVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_AVDO()
1587 return ((READ_BIT(PWR->VOSSR, PWR_VOSSR_ACTVOSRDY) == (PWR_VOSSR_ACTVOSRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_ACTVOS()
1598 return ((READ_BIT(PWR->VMSR, PWR_VMSR_USB33RDY) == (PWR_VMSR_USB33RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDUSB()
1609 return ((READ_BIT(PWR->VMCR, PWR_VMSR_VDDIO2RDY) == (PWR_VMSR_VDDIO2RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VDDIO2()
1619 return ((READ_BIT(PWR->BDSR, PWR_BDSR_BRRDY) == (PWR_BDSR_BRRDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_BRR()
1629 return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATL) == (PWR_BDSR_VBATL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATL()
1639 return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VBATH()
1650 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPL()
1661 return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_TEMPH()
1671 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
1681 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1691 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1701 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
1711 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU5()
1722 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU6()
1734 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU7()
1746 return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU8()
1757 WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF); in LL_PWR_ClearFlag_STOP()
1767 WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF); in LL_PWR_ClearFlag_SB()
1777 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1); in LL_PWR_ClearFlag_WU1()
1787 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2); in LL_PWR_ClearFlag_WU2()
1797 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3); in LL_PWR_ClearFlag_WU3()
1807 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4); in LL_PWR_ClearFlag_WU4()
1817 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5); in LL_PWR_ClearFlag_WU5()
1828 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6); in LL_PWR_ClearFlag_WU6()
1840 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7); in LL_PWR_ClearFlag_WU7()
1852 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8); in LL_PWR_ClearFlag_WU8()
1863 WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); in LL_PWR_ClearFlag_WU()
1881 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); in LL_PWR_EnableNSecurePrivilege()
1891 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); in LL_PWR_DisableNSecurePrivilege()
1901 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL); in LL_PWR_IsEnabledNSecurePrivilege()
1911 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV); in LL_PWR_EnableNSecurePrivilege()
1921 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV); in LL_PWR_DisableNSecurePrivilege()
1931 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_PRIV) == PWR_PRIVCFGR_PRIV) ? 1UL : 0UL); in LL_PWR_IsEnabledNSecurePrivilege()
1943 SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); in LL_PWR_EnableSecurePrivilege()
1953 CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); in LL_PWR_DisableSecurePrivilege()
1965 return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL); in LL_PWR_IsEnabledSecurePrivilege()
2005 WRITE_REG(PWR->SECCFGR, SecureConfig); in LL_PWR_ConfigSecure()
2041 return (READ_REG(PWR->SECCFGR)); in LL_PWR_GetConfigSecure()