309   MODIFY_REG(PWR->PMCR, PWR_PMCR_LPMS, Mode);  in LL_PWR_SetPowerMode()
321   return (READ_BIT(PWR->PMCR, PWR_PMCR_LPMS));  in LL_PWR_GetPowerMode()
335   MODIFY_REG(PWR->PMCR, PWR_PMCR_SVOS, VoltageScaling);  in LL_PWR_SetStopModeRegulVoltageScaling()
348   return (uint32_t)(READ_BIT(PWR->PMCR, PWR_PMCR_SVOS));  in LL_PWR_GetStopModeRegulVoltageScaling()
358   SET_BIT(PWR->PMCR, PWR_PMCR_FLPS);  in LL_PWR_EnableFlashPowerDown()
368   CLEAR_BIT(PWR->PMCR, PWR_PMCR_FLPS);  in LL_PWR_DisableFlashPowerDown()
378   return ((READ_BIT(PWR->PMCR, PWR_PMCR_FLPS) == (PWR_PMCR_FLPS)) ? 1UL : 0UL);  in LL_PWR_IsEnabledFlashPowerDown()
388   SET_BIT(PWR->PMCR, PWR_PMCR_BOOSTE);  in LL_PWR_EnableAnalogBooster()
398   CLEAR_BIT(PWR->PMCR, PWR_PMCR_BOOSTE);  in LL_PWR_DisableAnalogBooster()
408   return ((READ_BIT(PWR->PMCR, PWR_PMCR_BOOSTE) == (PWR_PMCR_BOOSTE)) ? 1UL : 0UL);  in LL_PWR_IsEnabledAnalogBooster()
418   SET_BIT(PWR->PMCR, PWR_PMCR_AVD_READY);  in LL_PWR_EnableAnalogVoltageReady()
428   CLEAR_BIT(PWR->PMCR, PWR_PMCR_AVD_READY);  in LL_PWR_DisableAnalogVoltageReady()
438   return ((READ_BIT(PWR->PMCR, PWR_PMCR_AVD_READY) == (PWR_PMCR_AVD_READY)) ? 1UL : 0UL);  in LL_PWR_IsEnabledAnalogVoltageReady()
448   SET_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO);  in LL_PWR_EnableAHBRAM1ShutOff()
458   CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO);  in LL_PWR_DisableAHBRAM1ShutOff()
468   return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM1SO) == (PWR_PMCR_SRAM1SO)) ? 1UL : 0UL);  in LL_PWR_IsEnabledAHBRAM1ShutOff()
478   SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO);  in LL_PWR_EnableAHBRAM2_48K_ShutOff()
488   CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO);  in LL_PWR_DisableAHBRAM2_48K_ShutOff()
498   return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_48SO) == (PWR_PMCR_SRAM2_48SO)) ? 1UL : 0UL);  in LL_PWR_IsEnabledAHBRAM2_48K_ShutOff()
510   SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO);  in LL_PWR_EnableAHBRAM2_16K_ShutOff()
520   CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO);  in LL_PWR_DisableAHBRAM2_16K_ShutOff()
530   return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16SO) == (PWR_PMCR_SRAM2_16SO)) ? 1UL : 0UL);  in LL_PWR_IsEnabledAHBRAM2_16K_ShutOff()
542   SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO);  in LL_PWR_EnableAHBRAM2_High_16K_ShutOff()
552   CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO);  in LL_PWR_DisableAHBRAM2_High_16K_ShutOff()
562   return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16HSO) == (PWR_PMCR_SRAM2_16HSO)) ? 1UL : 0UL);  in LL_PWR_IsEnabledAHBRAM2_High_16K_ShutOff()
574   SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO);  in LL_PWR_EnableAHBRAM2_Low_16K_ShutOff()
584   CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO);  in LL_PWR_DisableAHBRAM2_Low_16K_ShutOff()
594   return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2_16LSO) == (PWR_PMCR_SRAM2_16LSO)) ? 1UL : 0UL);  in LL_PWR_IsEnabledAHBRAM2_Low_16K_ShutOff()
606   SET_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO);  in LL_PWR_EnableAHBRAM2ShutOff()
616   CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO);  in LL_PWR_DisableAHBRAM2ShutOff()
626   return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM2SO) == (PWR_PMCR_SRAM2SO)) ? 1UL : 0UL);  in LL_PWR_IsEnabledAHBRAM2ShutOff()
638   SET_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO);  in LL_PWR_EnableAHBRAM3ShutOff()
648   CLEAR_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO);  in LL_PWR_DisableAHBRAM3ShutOff()
658   return ((READ_BIT(PWR->PMCR, PWR_PMCR_SRAM3SO) == (PWR_PMCR_SRAM3SO)) ? 1UL : 0UL);  in LL_PWR_IsEnabledAHBRAM3ShutOff()
670   SET_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO);  in LL_PWR_EnableETHERNETRAMShutOff()
680   CLEAR_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO);  in LL_PWR_DisableETHERNETRAMShutOff()
690   return ((READ_BIT(PWR->PMCR, PWR_PMCR_ETHERNETSO) == (PWR_PMCR_ETHERNETSO)) ? 1UL : 0UL);  in LL_PWR_IsEnabledETHERNETRAMShutOff()
1757   WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF);  in LL_PWR_ClearFlag_STOP()
1767   WRITE_REG(PWR->PMCR, PWR_PMCR_CSSF);  in LL_PWR_ClearFlag_SB()