Lines Matching refs:CFGR1

300   MODIFY_REG(COMPx->CFGR1, COMP_CFGR1_PWRMODE, PowerMode);  in LL_COMP_SetPowerMode()
314 return (uint32_t)(READ_BIT(COMPx->CFGR1, COMP_CFGR1_PWRMODE)); in LL_COMP_GetPowerMode()
370 MODIFY_REG(COMPx->CFGR1, in LL_COMP_ConfigInputs()
392 MODIFY_REG(COMPx->CFGR1, COMP_CFGR1_INPSEL1 | COMP_CFGR1_INPSEL2, InputPlus); in LL_COMP_SetInputPlus()
411 val = (uint32_t)(READ_BIT(COMPx->CFGR1, COMP_CFGR1_INPSEL1 | COMP_CFGR1_INPSEL2)); in LL_COMP_GetInputPlus()
453 MODIFY_REG(COMPx->CFGR1, COMP_CFGR1_INMSEL | COMP_CFGR1_SCALEN | COMP_CFGR1_BRGEN, InputMinus); in LL_COMP_SetInputMinus()
479 …return (uint32_t)(READ_BIT(COMPx->CFGR1, COMP_CFGR1_INMSEL | COMP_CFGR1_SCALEN | COMP_CFGR1_BRGEN)… in LL_COMP_GetInputMinus()
495 MODIFY_REG(COMPx->CFGR1, COMP_CFGR1_HYST, InputHysteresis); in LL_COMP_SetInputHysteresis()
510 return (uint32_t)(READ_BIT(COMPx->CFGR1, COMP_CFGR1_HYST)); in LL_COMP_GetInputHysteresis()
532 MODIFY_REG(COMPx->CFGR1, COMP_CFGR1_POLARITY, OutputPolarity); in LL_COMP_SetOutputPolarity()
545 return (uint32_t)(READ_BIT(COMPx->CFGR1, COMP_CFGR1_POLARITY)); in LL_COMP_GetOutputPolarity()
568 MODIFY_REG(COMPx->CFGR1, COMP_CFGR1_BLANKING, BlankingSource); in LL_COMP_SetOutputBlankingSource()
590 return (uint32_t)(READ_BIT(COMPx->CFGR1, COMP_CFGR1_BLANKING)); in LL_COMP_GetOutputBlankingSource()
612 SET_BIT(COMPx->CFGR1, COMP_CFGR1_EN); in LL_COMP_Enable()
623 CLEAR_BIT(COMPx->CFGR1, COMP_CFGR1_EN); in LL_COMP_Disable()
635 return ((READ_BIT(COMPx->CFGR1, COMP_CFGR1_EN) == (COMP_CFGR1_EN)) ? 1UL : 0UL); in LL_COMP_IsEnabled()
648 SET_BIT(COMPx->CFGR1, COMP_CFGR1_LOCK); in LL_COMP_Lock()
662 return ((READ_BIT(COMPx->CFGR1, COMP_CFGR1_LOCK) == (COMP_CFGR1_LOCK)) ? 1UL : 0UL); in LL_COMP_IsLocked()
736 SET_BIT(COMPx->CFGR1, COMP_CFGR1_ITEN); in LL_COMP_EnableIT_OutputTrig()
747 CLEAR_BIT(COMPx->CFGR1, COMP_CFGR1_ITEN); in LL_COMP_DisableIT_OutputTrig()
758 return ((READ_BIT(COMPx->CFGR1, COMP_CFGR1_ITEN) == (COMP_CFGR1_ITEN)) ? 1UL : 0UL); in LL_COMP_IsEnabledIT_OutputTrig()