Lines Matching full:mode
56 uint32_t MemoryMode; /*!< It Specifies the memory mode.
135 used for memory-mapped mode).
141 uint32_t InstructionMode; /*!< It indicates the mode of the instruction.
145 uint32_t InstructionDTRMode; /*!< It enables or not the DTR mode for the instruction phase.
149 …uint32_t AddressMode; /*!< It indicates the address mode. Address mode precises numb…
154 uint32_t AddressDTRMode; /*!< It enables or not the DTR mode for the address phase.
158 uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes.
162 …uint32_t AlternateBytesDTRMode; /*!< It enables or not the DTR mode for the alternate bytes ph…
164 …uint32_t DataMode; /*!< It indicates the data mode. Data mode precises number of …
168 This field is only used for indirect mode.
170 uint32_t DataDTRMode; /*!< It enables or not the DTR mode for the data phase.
176 uint32_t SIOOMode; /*!< It enables or not the SIOO mode. When SIOO mode enabled,
191 uint32_t LatencyMode; /*!< It configures the latency mode.
207 This field is only used for indirect mode.
209 In case of autopolling mode, this parameter can be
216 * @brief HAL XSPI Auto Polling mode configuration structure definition
235 * @brief HAL XSPI Memory Mapped mode configuration structure definition
286 …HYPERBUS_INIT (0x00000001U) /*!< Initialization done in hyperbus mode but timing configur…
317 /** @defgroup XSPI_MemoryMode XSPI Memory Mode
320 #define HAL_XSPI_SINGLE_MEM (0x00000000U) /*!< Dual-memory mode disabled */
321 #define HAL_XSPI_DUAL_MEM (XSPI_CR_DMM) /*!< Dual mode enabled */
330 …L_XSPI_MEMTYPE_MICRON (0x00000000U) /*!< Micron mode */
331 …L_XSPI_MEMTYPE_MACRONIX (XSPI_DCR1_MTYP_0) /*!< Macronix mode */
332 …L_XSPI_MEMTYPE_APMEM (XSPI_DCR1_MTYP_1) /*!< AP Memory mode */
333 …L_XSPI_MEMTYPE_MACRONIX_RAM ((XSPI_DCR1_MTYP_1 | XSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode*/
334 …L_XSPI_MEMTYPE_HYPERBUS (XSPI_DCR1_MTYP_2) /*!< Hyperbus mode */
335 …L_XSPI_MEMTYPE_APMEM_16BITS ((XSPI_DCR1_MTYP_2 | XSPI_DCR1_MTYP_1)) /*!< AP Memory mode */
389 /** @defgroup XSPI_ClockMode XSPI Clock Mode
479 …PE_COMMON_CFG (0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */
480 …PE_READ_CFG (0x00000001U) /*!< Read configuration (memory-mapped mode) */
481 …PE_WRITE_CFG (0x00000002U) /*!< Write configuration (memory-mapped mode) */
482 …PE_WRAP_CFG (0x00000003U) /*!< Wrap configuration (memory-mapped mode) */
498 /** @defgroup XSPI_InstructionMode XSPI Instruction Mode
521 /** @defgroup XSPI_InstructionDTRMode XSPI Instruction DTR Mode
524 #define HAL_XSPI_INSTRUCTION_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for …
525 #define HAL_XSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)XSPI_CCR_IDTR) /*!< DTR mode enabled for i…
530 /** @defgroup XSPI_AddressMode XSPI Address Mode
553 /** @defgroup XSPI_AddressDTRMode XSPI Address DTR Mode
556 #define HAL_XSPI_ADDRESS_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for…
557 #define HAL_XSPI_ADDRESS_DTR_ENABLE ((uint32_t)XSPI_CCR_ADDTR) /*!< DTR mode enabled for …
562 /** @defgroup XSPI_AlternateBytesMode XSPI Alternate Bytes Mode
585 /** @defgroup XSPI_AlternateBytesDTRMode XSPI Alternate Bytes DTR Mode
588 #define HAL_XSPI_ALT_BYTES_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for…
589 #define HAL_XSPI_ALT_BYTES_DTR_ENABLE ((uint32_t)XSPI_CCR_ABDTR) /*!< DTR mode enabled for …
594 /** @defgroup XSPI_DataMode XSPI Data Mode
606 /** @defgroup XSPI_DataDTRMode XSPI Data DTR Mode
609 #define HAL_XSPI_DATA_DTR_DISABLE (0x00000000U) /*!< DTR mode disabled for …
610 #define HAL_XSPI_DATA_DTR_ENABLE ((uint32_t)XSPI_CCR_DDTR) /*!< DTR mode enabled for d…
615 /** @defgroup XSPI_DQSMode XSPI DQS Mode
624 /** @defgroup XSPI_SIOOMode XSPI SIOO Mode
642 /** @defgroup XSPI_LatencyMode XSPI Hyperbus Latency Mode
654 …e HAL_XSPI_MEMORY_ADDRESS_SPACE (0x00000000U) /*!< HyperBus memory mode */
655 …e HAL_XSPI_REGISTER_ADDRESS_SPACE ((uint32_t)XSPI_DCR1_MTYP_0) /*!< HyperBus register mode */
660 /** @defgroup XSPI_MatchMode XSPI Match Mode
663 #define HAL_XSPI_MATCH_MODE_AND (0x00000000U) /*!< AND match mode between u…
664 #define HAL_XSPI_MATCH_MODE_OR ((uint32_t)XSPI_CR_PMM) /*!< OR match mode between un…
691 … XSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode …
692 …SPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode …
860 /* XSPI indirect mode functions */
868 /* XSPI status flag polling mode functions */
873 /* XSPI memory-mapped mode functions */
881 /* XSPI indirect mode Callback functions */
888 /* XSPI status flag polling mode functions */
891 /* XSPI memory-mapped mode functions */
949 #define IS_XSPI_MEMORY_MODE(MODE) (((MODE) == HAL_XSPI_SINGLE_MEM) || \ argument
950 ((MODE) == HAL_XSPI_DUAL_MEM))
997 #define IS_XSPI_CLOCK_MODE(MODE) (((MODE) == HAL_XSPI_CLOCK_MODE_0) || \ argument
998 ((MODE) == HAL_XSPI_CLOCK_MODE_3))
1062 #define IS_XSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_NONE) || \ argument
1063 ((MODE) == HAL_XSPI_INSTRUCTION_1_LINE) || \
1064 ((MODE) == HAL_XSPI_INSTRUCTION_2_LINES) || \
1065 ((MODE) == HAL_XSPI_INSTRUCTION_4_LINES) || \
1066 ((MODE) == HAL_XSPI_INSTRUCTION_8_LINES))
1073 #define IS_XSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_XSPI_INSTRUCTION_DTR_DISABLE) || \ argument
1074 ((MODE) == HAL_XSPI_INSTRUCTION_DTR_ENABLE))
1076 #define IS_XSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_NONE) || \ argument
1077 ((MODE) == HAL_XSPI_ADDRESS_1_LINE) || \
1078 ((MODE) == HAL_XSPI_ADDRESS_2_LINES) || \
1079 ((MODE) == HAL_XSPI_ADDRESS_4_LINES) || \
1080 ((MODE) == HAL_XSPI_ADDRESS_8_LINES))
1087 #define IS_XSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ADDRESS_DTR_DISABLE) || \ argument
1088 ((MODE) == HAL_XSPI_ADDRESS_DTR_ENABLE))
1090 #define IS_XSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_NONE) || \ argument
1091 ((MODE) == HAL_XSPI_ALT_BYTES_1_LINE) || \
1092 ((MODE) == HAL_XSPI_ALT_BYTES_2_LINES) || \
1093 ((MODE) == HAL_XSPI_ALT_BYTES_4_LINES) || \
1094 ((MODE) == HAL_XSPI_ALT_BYTES_8_LINES))
1101 #define IS_XSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_XSPI_ALT_BYTES_DTR_DISABLE) || \ argument
1102 ((MODE) == HAL_XSPI_ALT_BYTES_DTR_ENABLE))
1104 #define IS_XSPI_DATA_MODE(MODE) (((MODE) == HAL_XSPI_DATA_NONE) || \ argument
1105 ((MODE) == HAL_XSPI_DATA_1_LINE) || \
1106 ((MODE) == HAL_XSPI_DATA_2_LINES) || \
1107 ((MODE) == HAL_XSPI_DATA_4_LINES) || \
1108 ((MODE) == HAL_XSPI_DATA_8_LINES))
1112 #define IS_XSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_XSPI_DATA_DTR_DISABLE) || \ argument
1113 ((MODE) == HAL_XSPI_DATA_DTR_ENABLE))
1117 #define IS_XSPI_DQS_MODE(MODE) (((MODE) == HAL_XSPI_DQS_DISABLE) || \ argument
1118 ((MODE) == HAL_XSPI_DQS_ENABLE))
1120 #define IS_XSPI_SIOO_MODE(MODE) (((MODE) == HAL_XSPI_SIOO_INST_EVERY_CMD) || \ argument
1121 ((MODE) == HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD))
1127 #define IS_XSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_XSPI_LATENCY_ON_WRITE) || \ argument
1128 ((MODE) == HAL_XSPI_NO_LATENCY_ON_WRITE))
1130 #define IS_XSPI_LATENCY_MODE(MODE) (((MODE) == HAL_XSPI_VARIABLE_LATENCY) || \ argument
1131 ((MODE) == HAL_XSPI_FIXED_LATENCY))
1136 #define IS_XSPI_MATCH_MODE(MODE) (((MODE) == HAL_XSPI_MATCH_MODE_AND) || \ argument
1137 ((MODE) == HAL_XSPI_MATCH_MODE_OR))
1139 #define IS_XSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_XSPI_AUTOMATIC_STOP_ENABLE) || \ argument
1140 ((MODE) == HAL_XSPI_AUTOMATIC_STOP_DISABLE))
1146 #define IS_XSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_XSPI_TIMEOUT_COUNTER_DISABLE) || \ argument
1147 ((MODE) == HAL_XSPI_TIMEOUT_COUNTER_ENABLE))