625   uint32_t tmpcr2;  in LL_TIM_HALLSENSOR_Init()  local
640   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in LL_TIM_HALLSENSOR_Init()
652   tmpcr2 |= TIM_CR2_TI1S;  in LL_TIM_HALLSENSOR_Init()
655   tmpcr2 |= LL_TIM_TRGO_OC2REF;  in LL_TIM_HALLSENSOR_Init()
678   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in LL_TIM_HALLSENSOR_Init()
809   uint32_t tmpcr2;  in OC1Config()  local
824   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC1Config()
855     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);  in OC1Config()
858     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);  in OC1Config()
862   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC1Config()
888   uint32_t tmpcr2;  in OC2Config()  local
903   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC2Config()
934     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);  in OC2Config()
937     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);  in OC2Config()
941   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC2Config()
967   uint32_t tmpcr2;  in OC3Config()  local
982   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC3Config()
1013     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);  in OC3Config()
1016     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);  in OC3Config()
1020   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC3Config()
1046   uint32_t tmpcr2;  in OC4Config()  local
1061   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);  in OC4Config()
1092     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);  in OC4Config()
1095     MODIFY_REG(tmpcr2, TIM_CR2_OIS4N, TIM_OCInitStruct->OCNIdleState << 7U);  in OC4Config()
1099   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC4Config()