548   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
554   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
581   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
637   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
646   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
687   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
818   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
821   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
871   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
897   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
900   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
950   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
976   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
979   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1029   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1055   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1058   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1108   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1135   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1138   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1169   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1196   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1199   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1229   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1252   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1260   MODIFY_REG(TIMx->CCER,  in IC1Config()
1285   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1293   MODIFY_REG(TIMx->CCER,  in IC2Config()
1318   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1326   MODIFY_REG(TIMx->CCER,  in IC3Config()
1351   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1359   MODIFY_REG(TIMx->CCER,  in IC4Config()