Lines Matching refs:htim
239 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
281 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Init() argument
284 if (htim == NULL) in HAL_TIM_Base_Init()
290 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Init()
291 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_Base_Init()
292 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_Base_Init()
293 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_Base_Init()
294 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_Base_Init()
296 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_Base_Init()
299 htim->Lock = HAL_UNLOCKED; in HAL_TIM_Base_Init()
303 TIM_ResetCallback(htim); in HAL_TIM_Base_Init()
305 if (htim->Base_MspInitCallback == NULL) in HAL_TIM_Base_Init()
307 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_Base_Init()
310 htim->Base_MspInitCallback(htim); in HAL_TIM_Base_Init()
313 HAL_TIM_Base_MspInit(htim); in HAL_TIM_Base_Init()
318 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Init()
321 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_Base_Init()
324 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_Base_Init()
327 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Base_Init()
328 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Base_Init()
331 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Init()
341 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_DeInit() argument
344 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_DeInit()
346 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_DeInit()
349 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_DeInit()
352 if (htim->Base_MspDeInitCallback == NULL) in HAL_TIM_Base_DeInit()
354 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_Base_DeInit()
357 htim->Base_MspDeInitCallback(htim); in HAL_TIM_Base_DeInit()
360 HAL_TIM_Base_MspDeInit(htim); in HAL_TIM_Base_DeInit()
364 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_Base_DeInit()
367 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Base_DeInit()
368 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Base_DeInit()
371 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_Base_DeInit()
374 __HAL_UNLOCK(htim); in HAL_TIM_Base_DeInit()
384 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_MspInit() argument
387 UNUSED(htim); in HAL_TIM_Base_MspInit()
399 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Base_MspDeInit() argument
402 UNUSED(htim); in HAL_TIM_Base_MspDeInit()
415 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Start() argument
420 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start()
423 if (htim->State != HAL_TIM_STATE_READY) in HAL_TIM_Base_Start()
429 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start()
432 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start()
434 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start()
437 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start()
442 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start()
454 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop() argument
457 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop()
460 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop()
463 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop()
474 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Start_IT() argument
479 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start_IT()
482 if (htim->State != HAL_TIM_STATE_READY) in HAL_TIM_Base_Start_IT()
488 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start_IT()
491 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); in HAL_TIM_Base_Start_IT()
494 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start_IT()
496 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start_IT()
499 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_IT()
504 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_IT()
516 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop_IT() argument
519 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop_IT()
522 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); in HAL_TIM_Base_Stop_IT()
525 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop_IT()
528 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop_IT()
541 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t L… in HAL_TIM_Base_Start_DMA() argument
546 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); in HAL_TIM_Base_Start_DMA()
549 if (htim->State == HAL_TIM_STATE_BUSY) in HAL_TIM_Base_Start_DMA()
553 else if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_Base_Start_DMA()
561 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Base_Start_DMA()
570 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_Base_Start_DMA()
571 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_Base_Start_DMA()
574 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Base_Start_DMA()
577 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->AR… in HAL_TIM_Base_Start_DMA()
585 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); in HAL_TIM_Base_Start_DMA()
588 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_Base_Start_DMA()
590 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_Base_Start_DMA()
593 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_DMA()
598 __HAL_TIM_ENABLE(htim); in HAL_TIM_Base_Start_DMA()
610 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) in HAL_TIM_Base_Stop_DMA() argument
613 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); in HAL_TIM_Base_Stop_DMA()
616 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); in HAL_TIM_Base_Stop_DMA()
618 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_Base_Stop_DMA()
621 __HAL_TIM_DISABLE(htim); in HAL_TIM_Base_Stop_DMA()
624 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Base_Stop_DMA()
665 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) in HAL_TIM_OC_Init() argument
668 if (htim == NULL) in HAL_TIM_OC_Init()
674 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OC_Init()
675 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_OC_Init()
676 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_OC_Init()
677 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_OC_Init()
678 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_OC_Init()
680 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_OC_Init()
683 htim->Lock = HAL_UNLOCKED; in HAL_TIM_OC_Init()
687 TIM_ResetCallback(htim); in HAL_TIM_OC_Init()
689 if (htim->OC_MspInitCallback == NULL) in HAL_TIM_OC_Init()
691 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_OC_Init()
694 htim->OC_MspInitCallback(htim); in HAL_TIM_OC_Init()
697 HAL_TIM_OC_MspInit(htim); in HAL_TIM_OC_Init()
702 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OC_Init()
705 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_OC_Init()
708 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_OC_Init()
711 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Init()
712 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Init()
715 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OC_Init()
725 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_DeInit() argument
728 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OC_DeInit()
730 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OC_DeInit()
733 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_DeInit()
736 if (htim->OC_MspDeInitCallback == NULL) in HAL_TIM_OC_DeInit()
738 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_OC_DeInit()
741 htim->OC_MspDeInitCallback(htim); in HAL_TIM_OC_DeInit()
744 HAL_TIM_OC_MspDeInit(htim); in HAL_TIM_OC_DeInit()
748 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_OC_DeInit()
751 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OC_DeInit()
752 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OC_DeInit()
755 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_OC_DeInit()
758 __HAL_UNLOCK(htim); in HAL_TIM_OC_DeInit()
768 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_MspInit() argument
771 UNUSED(htim); in HAL_TIM_OC_MspInit()
783 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OC_MspDeInit() argument
786 UNUSED(htim); in HAL_TIM_OC_MspDeInit()
806 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Start() argument
811 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_OC_Start()
814 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start()
820 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start()
823 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start()
825 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start()
828 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start()
832 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start()
834 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start()
837 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start()
842 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start()
862 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop() argument
865 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_OC_Stop()
868 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop()
870 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop()
873 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop()
877 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop()
880 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop()
897 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Start_IT() argument
903 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Start_IT()
906 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start_IT()
912 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start_IT()
919 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OC_Start_IT()
926 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OC_Start_IT()
933 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_OC_Start_IT()
940 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_OC_Start_IT()
952 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start_IT()
954 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start_IT()
957 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start_IT()
961 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start_IT()
963 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start_IT()
966 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_IT()
971 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_IT()
990 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop_IT() argument
995 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Stop_IT()
1002 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OC_Stop_IT()
1009 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OC_Stop_IT()
1016 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_OC_Stop_IT()
1023 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_OC_Stop_IT()
1035 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop_IT()
1037 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop_IT()
1040 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop_IT()
1044 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop_IT()
1047 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop_IT()
1067 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *p… in HAL_TIM_OC_Start_DMA() argument
1074 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Start_DMA()
1077 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) in HAL_TIM_OC_Start_DMA()
1081 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_OC_Start_DMA()
1089 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OC_Start_DMA()
1102 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1103 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1106 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1109 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, in HAL_TIM_OC_Start_DMA()
1117 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_OC_Start_DMA()
1124 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1125 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1128 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1131 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, in HAL_TIM_OC_Start_DMA()
1139 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_OC_Start_DMA()
1146 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1147 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1150 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1153 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, in HAL_TIM_OC_Start_DMA()
1160 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_OC_Start_DMA()
1167 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_OC_Start_DMA()
1168 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_OC_Start_DMA()
1171 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_OC_Start_DMA()
1174 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, in HAL_TIM_OC_Start_DMA()
1181 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_OC_Start_DMA()
1193 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_OC_Start_DMA()
1195 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Start_DMA()
1198 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1202 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_OC_Start_DMA()
1204 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_OC_Start_DMA()
1207 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1212 __HAL_TIM_ENABLE(htim); in HAL_TIM_OC_Start_DMA()
1231 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_OC_Stop_DMA() argument
1236 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_OC_Stop_DMA()
1243 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_OC_Stop_DMA()
1244 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_OC_Stop_DMA()
1251 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_OC_Stop_DMA()
1252 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_OC_Stop_DMA()
1259 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_OC_Stop_DMA()
1260 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_OC_Stop_DMA()
1267 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_OC_Stop_DMA()
1268 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_OC_Stop_DMA()
1280 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_OC_Stop_DMA()
1282 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OC_Stop_DMA()
1285 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OC_Stop_DMA()
1289 __HAL_TIM_DISABLE(htim); in HAL_TIM_OC_Stop_DMA()
1292 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OC_Stop_DMA()
1334 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_Init() argument
1337 if (htim == NULL) in HAL_TIM_PWM_Init()
1343 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_PWM_Init()
1344 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_PWM_Init()
1345 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_PWM_Init()
1346 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_PWM_Init()
1347 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_PWM_Init()
1349 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_PWM_Init()
1352 htim->Lock = HAL_UNLOCKED; in HAL_TIM_PWM_Init()
1356 TIM_ResetCallback(htim); in HAL_TIM_PWM_Init()
1358 if (htim->PWM_MspInitCallback == NULL) in HAL_TIM_PWM_Init()
1360 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_PWM_Init()
1363 htim->PWM_MspInitCallback(htim); in HAL_TIM_PWM_Init()
1366 HAL_TIM_PWM_MspInit(htim); in HAL_TIM_PWM_Init()
1371 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_PWM_Init()
1374 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_PWM_Init()
1377 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_PWM_Init()
1380 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Init()
1381 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Init()
1384 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_PWM_Init()
1394 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_DeInit() argument
1397 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_PWM_DeInit()
1399 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_PWM_DeInit()
1402 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_DeInit()
1405 if (htim->PWM_MspDeInitCallback == NULL) in HAL_TIM_PWM_DeInit()
1407 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_PWM_DeInit()
1410 htim->PWM_MspDeInitCallback(htim); in HAL_TIM_PWM_DeInit()
1413 HAL_TIM_PWM_MspDeInit(htim); in HAL_TIM_PWM_DeInit()
1417 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_PWM_DeInit()
1420 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_PWM_DeInit()
1421 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_PWM_DeInit()
1424 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_PWM_DeInit()
1427 __HAL_UNLOCK(htim); in HAL_TIM_PWM_DeInit()
1437 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_MspInit() argument
1440 UNUSED(htim); in HAL_TIM_PWM_MspInit()
1452 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_MspDeInit() argument
1455 UNUSED(htim); in HAL_TIM_PWM_MspDeInit()
1475 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Start() argument
1480 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_PWM_Start()
1483 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start()
1489 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start()
1492 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start()
1494 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start()
1497 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start()
1501 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start()
1503 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start()
1506 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start()
1511 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start()
1531 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop() argument
1534 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_PWM_Stop()
1537 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop()
1539 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop()
1542 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop()
1546 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop()
1549 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop()
1566 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Start_IT() argument
1572 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Start_IT()
1575 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start_IT()
1581 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start_IT()
1588 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_PWM_Start_IT()
1595 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_PWM_Start_IT()
1602 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_PWM_Start_IT()
1609 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_PWM_Start_IT()
1621 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start_IT()
1623 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start_IT()
1626 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1630 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start_IT()
1632 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start_IT()
1635 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1640 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_IT()
1659 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop_IT() argument
1664 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Stop_IT()
1671 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_PWM_Stop_IT()
1678 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_PWM_Stop_IT()
1685 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_PWM_Stop_IT()
1692 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_PWM_Stop_IT()
1704 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop_IT()
1706 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop_IT()
1709 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop_IT()
1713 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop_IT()
1716 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop_IT()
1736 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *… in HAL_TIM_PWM_Start_DMA() argument
1743 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Start_DMA()
1746 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) in HAL_TIM_PWM_Start_DMA()
1750 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) in HAL_TIM_PWM_Start_DMA()
1758 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_PWM_Start_DMA()
1771 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1772 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1775 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1778 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, in HAL_TIM_PWM_Start_DMA()
1786 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_PWM_Start_DMA()
1793 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1794 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1797 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1800 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, in HAL_TIM_PWM_Start_DMA()
1807 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_PWM_Start_DMA()
1814 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1815 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1818 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1821 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, in HAL_TIM_PWM_Start_DMA()
1828 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_PWM_Start_DMA()
1835 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_PWM_Start_DMA()
1836 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_PWM_Start_DMA()
1839 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_PWM_Start_DMA()
1842 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, in HAL_TIM_PWM_Start_DMA()
1849 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_PWM_Start_DMA()
1861 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_PWM_Start_DMA()
1863 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Start_DMA()
1866 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1870 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_PWM_Start_DMA()
1872 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_PWM_Start_DMA()
1875 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1880 __HAL_TIM_ENABLE(htim); in HAL_TIM_PWM_Start_DMA()
1899 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_PWM_Stop_DMA() argument
1904 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_PWM_Stop_DMA()
1911 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_PWM_Stop_DMA()
1912 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_PWM_Stop_DMA()
1919 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_PWM_Stop_DMA()
1920 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_PWM_Stop_DMA()
1927 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_PWM_Stop_DMA()
1928 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_PWM_Stop_DMA()
1935 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_PWM_Stop_DMA()
1936 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_PWM_Stop_DMA()
1948 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_PWM_Stop_DMA()
1950 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_PWM_Stop_DMA()
1953 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_PWM_Stop_DMA()
1957 __HAL_TIM_DISABLE(htim); in HAL_TIM_PWM_Stop_DMA()
1960 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_PWM_Stop_DMA()
2002 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) in HAL_TIM_IC_Init() argument
2005 if (htim == NULL) in HAL_TIM_IC_Init()
2011 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_IC_Init()
2012 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_IC_Init()
2013 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_IC_Init()
2014 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_IC_Init()
2015 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_IC_Init()
2017 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_IC_Init()
2020 htim->Lock = HAL_UNLOCKED; in HAL_TIM_IC_Init()
2024 TIM_ResetCallback(htim); in HAL_TIM_IC_Init()
2026 if (htim->IC_MspInitCallback == NULL) in HAL_TIM_IC_Init()
2028 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_IC_Init()
2031 htim->IC_MspInitCallback(htim); in HAL_TIM_IC_Init()
2034 HAL_TIM_IC_MspInit(htim); in HAL_TIM_IC_Init()
2039 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_IC_Init()
2042 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_IC_Init()
2045 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_IC_Init()
2048 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Init()
2049 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Init()
2052 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_IC_Init()
2062 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_DeInit() argument
2065 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_IC_DeInit()
2067 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_IC_DeInit()
2070 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_DeInit()
2073 if (htim->IC_MspDeInitCallback == NULL) in HAL_TIM_IC_DeInit()
2075 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_IC_DeInit()
2078 htim->IC_MspDeInitCallback(htim); in HAL_TIM_IC_DeInit()
2081 HAL_TIM_IC_MspDeInit(htim); in HAL_TIM_IC_DeInit()
2085 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_IC_DeInit()
2088 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_IC_DeInit()
2089 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_IC_DeInit()
2092 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_IC_DeInit()
2095 __HAL_UNLOCK(htim); in HAL_TIM_IC_DeInit()
2105 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_MspInit() argument
2108 UNUSED(htim); in HAL_TIM_IC_MspInit()
2120 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_IC_MspDeInit() argument
2123 UNUSED(htim); in HAL_TIM_IC_MspDeInit()
2141 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Start() argument
2144 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start()
2145 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start()
2148 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start()
2158 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start()
2159 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start()
2162 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start()
2165 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start()
2167 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start()
2170 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start()
2175 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start()
2193 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop() argument
2196 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop()
2199 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop()
2202 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop()
2205 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop()
2206 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop()
2223 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Start_IT() argument
2228 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_IT()
2229 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_IT()
2232 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start_IT()
2242 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_IT()
2243 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_IT()
2250 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_IC_Start_IT()
2257 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_IC_Start_IT()
2264 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_IC_Start_IT()
2271 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_IC_Start_IT()
2283 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start_IT()
2286 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start_IT()
2288 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start_IT()
2291 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_IT()
2296 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_IT()
2315 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop_IT() argument
2320 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop_IT()
2327 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_IC_Stop_IT()
2334 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_IC_Stop_IT()
2341 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); in HAL_TIM_IC_Stop_IT()
2348 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); in HAL_TIM_IC_Stop_IT()
2360 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop_IT()
2363 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop_IT()
2366 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_IT()
2367 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_IT()
2387 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, … in HAL_TIM_IC_Start_DMA() argument
2392 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_DMA()
2393 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); in HAL_TIM_IC_Start_DMA()
2396 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Start_DMA()
2397 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); in HAL_TIM_IC_Start_DMA()
2414 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_DMA()
2415 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_IC_Start_DMA()
2424 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); in HAL_TIM_IC_Start_DMA()
2431 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2432 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2435 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2438 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2445 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_IC_Start_DMA()
2452 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2453 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2456 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2459 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2466 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_IC_Start_DMA()
2473 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2474 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2477 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2480 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2487 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_IC_Start_DMA()
2494 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_IC_Start_DMA()
2495 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_IC_Start_DMA()
2498 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_IC_Start_DMA()
2501 … if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, in HAL_TIM_IC_Start_DMA()
2508 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_IC_Start_DMA()
2518 if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) in HAL_TIM_IC_Start_DMA()
2520 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; in HAL_TIM_IC_Start_DMA()
2523 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_DMA()
2528 __HAL_TIM_ENABLE(htim); in HAL_TIM_IC_Start_DMA()
2546 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_IC_Stop_DMA() argument
2551 assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); in HAL_TIM_IC_Stop_DMA()
2552 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); in HAL_TIM_IC_Stop_DMA()
2555 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); in HAL_TIM_IC_Stop_DMA()
2562 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_IC_Stop_DMA()
2563 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_IC_Stop_DMA()
2570 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_IC_Stop_DMA()
2571 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_IC_Stop_DMA()
2578 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); in HAL_TIM_IC_Stop_DMA()
2579 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_IC_Stop_DMA()
2586 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); in HAL_TIM_IC_Stop_DMA()
2587 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_IC_Stop_DMA()
2599 __HAL_TIM_DISABLE(htim); in HAL_TIM_IC_Stop_DMA()
2602 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_DMA()
2603 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_IC_Stop_DMA()
2651 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) in HAL_TIM_OnePulse_Init() argument
2654 if (htim == NULL) in HAL_TIM_OnePulse_Init()
2660 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_Init()
2661 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_OnePulse_Init()
2662 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_OnePulse_Init()
2664 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_OnePulse_Init()
2665 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_OnePulse_Init()
2667 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_OnePulse_Init()
2670 htim->Lock = HAL_UNLOCKED; in HAL_TIM_OnePulse_Init()
2674 TIM_ResetCallback(htim); in HAL_TIM_OnePulse_Init()
2676 if (htim->OnePulse_MspInitCallback == NULL) in HAL_TIM_OnePulse_Init()
2678 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_OnePulse_Init()
2681 htim->OnePulse_MspInitCallback(htim); in HAL_TIM_OnePulse_Init()
2684 HAL_TIM_OnePulse_MspInit(htim); in HAL_TIM_OnePulse_Init()
2689 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_Init()
2692 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_OnePulse_Init()
2695 htim->Instance->CR1 &= ~TIM_CR1_OPM; in HAL_TIM_OnePulse_Init()
2698 htim->Instance->CR1 |= OnePulseMode; in HAL_TIM_OnePulse_Init()
2701 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_OnePulse_Init()
2704 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2705 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2706 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2707 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Init()
2710 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OnePulse_Init()
2720 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_DeInit() argument
2723 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_DeInit()
2725 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_DeInit()
2728 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_DeInit()
2731 if (htim->OnePulse_MspDeInitCallback == NULL) in HAL_TIM_OnePulse_DeInit()
2733 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_OnePulse_DeInit()
2736 htim->OnePulse_MspDeInitCallback(htim); in HAL_TIM_OnePulse_DeInit()
2739 HAL_TIM_OnePulse_MspDeInit(htim); in HAL_TIM_OnePulse_DeInit()
2743 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_OnePulse_DeInit()
2746 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2747 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2748 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2749 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_OnePulse_DeInit()
2752 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_OnePulse_DeInit()
2755 __HAL_UNLOCK(htim); in HAL_TIM_OnePulse_DeInit()
2765 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_MspInit() argument
2768 UNUSED(htim); in HAL_TIM_OnePulse_MspInit()
2780 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_MspDeInit() argument
2783 UNUSED(htim); in HAL_TIM_OnePulse_MspDeInit()
2800 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Start() argument
2802 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_OnePulse_Start()
2803 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_OnePulse_Start()
2804 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start()
2805 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start()
2820 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2821 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2822 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2823 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start()
2834 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start()
2835 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start()
2837 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Start()
2840 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OnePulse_Start()
2857 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Stop() argument
2868 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop()
2869 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop()
2871 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Stop()
2874 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OnePulse_Stop()
2878 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_Stop()
2881 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2882 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2883 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2884 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop()
2900 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Start_IT() argument
2902 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_OnePulse_Start_IT()
2903 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_OnePulse_Start_IT()
2904 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start_IT()
2905 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_OnePulse_Start_IT()
2920 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2921 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2922 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2923 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_OnePulse_Start_IT()
2935 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OnePulse_Start_IT()
2938 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OnePulse_Start_IT()
2940 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start_IT()
2941 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_OnePulse_Start_IT()
2943 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Start_IT()
2946 __HAL_TIM_MOE_ENABLE(htim); in HAL_TIM_OnePulse_Start_IT()
2963 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) in HAL_TIM_OnePulse_Stop_IT() argument
2969 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_OnePulse_Stop_IT()
2972 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_OnePulse_Stop_IT()
2979 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop_IT()
2980 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_OnePulse_Stop_IT()
2982 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) in HAL_TIM_OnePulse_Stop_IT()
2985 __HAL_TIM_MOE_DISABLE(htim); in HAL_TIM_OnePulse_Stop_IT()
2989 __HAL_TIM_DISABLE(htim); in HAL_TIM_OnePulse_Stop_IT()
2992 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
2993 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
2994 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
2995 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_OnePulse_Stop_IT()
3042 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sCon… in HAL_TIM_Encoder_Init() argument
3049 if (htim == NULL) in HAL_TIM_Encoder_Init()
3055 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Init()
3056 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); in HAL_TIM_Encoder_Init()
3057 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); in HAL_TIM_Encoder_Init()
3058 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); in HAL_TIM_Encoder_Init()
3068 assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); in HAL_TIM_Encoder_Init()
3070 if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_Encoder_Init()
3073 htim->Lock = HAL_UNLOCKED; in HAL_TIM_Encoder_Init()
3077 TIM_ResetCallback(htim); in HAL_TIM_Encoder_Init()
3079 if (htim->Encoder_MspInitCallback == NULL) in HAL_TIM_Encoder_Init()
3081 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_Encoder_Init()
3084 htim->Encoder_MspInitCallback(htim); in HAL_TIM_Encoder_Init()
3087 HAL_TIM_Encoder_MspInit(htim); in HAL_TIM_Encoder_Init()
3092 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Encoder_Init()
3095 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); in HAL_TIM_Encoder_Init()
3098 TIM_Base_SetConfig(htim->Instance, &htim->Init); in HAL_TIM_Encoder_Init()
3101 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_Encoder_Init()
3104 tmpccmr1 = htim->Instance->CCMR1; in HAL_TIM_Encoder_Init()
3107 tmpccer = htim->Instance->CCER; in HAL_TIM_Encoder_Init()
3128 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_Encoder_Init()
3131 htim->Instance->CCMR1 = tmpccmr1; in HAL_TIM_Encoder_Init()
3134 htim->Instance->CCER = tmpccer; in HAL_TIM_Encoder_Init()
3137 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_Encoder_Init()
3140 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3141 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3142 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3143 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Init()
3146 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_Encoder_Init()
3157 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_DeInit() argument
3160 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_DeInit()
3162 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_Encoder_DeInit()
3165 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_DeInit()
3168 if (htim->Encoder_MspDeInitCallback == NULL) in HAL_TIM_Encoder_DeInit()
3170 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_Encoder_DeInit()
3173 htim->Encoder_MspDeInitCallback(htim); in HAL_TIM_Encoder_DeInit()
3176 HAL_TIM_Encoder_MspDeInit(htim); in HAL_TIM_Encoder_DeInit()
3180 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; in HAL_TIM_Encoder_DeInit()
3183 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3184 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3185 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3186 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); in HAL_TIM_Encoder_DeInit()
3189 htim->State = HAL_TIM_STATE_RESET; in HAL_TIM_Encoder_DeInit()
3192 __HAL_UNLOCK(htim); in HAL_TIM_Encoder_DeInit()
3202 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_MspInit() argument
3205 UNUSED(htim); in HAL_TIM_Encoder_MspInit()
3217 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_MspDeInit() argument
3220 UNUSED(htim); in HAL_TIM_Encoder_MspDeInit()
3237 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Start() argument
3239 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start()
3240 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start()
3241 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start()
3242 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start()
3245 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start()
3257 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3258 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3270 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3271 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3285 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3286 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3287 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3288 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start()
3297 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3303 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3309 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3310 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start()
3315 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start()
3331 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop() argument
3334 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop()
3342 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3348 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3354 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3355 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop()
3361 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop()
3366 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3367 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3371 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3372 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3373 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3374 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop()
3391 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Start_IT() argument
3393 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start_IT()
3394 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start_IT()
3395 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_IT()
3396 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_IT()
3399 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start_IT()
3411 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3412 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3424 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3425 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3439 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3440 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3441 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3442 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_IT()
3452 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3453 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Start_IT()
3459 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3460 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Start_IT()
3466 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3467 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_IT()
3468 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Start_IT()
3469 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Start_IT()
3475 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_IT()
3491 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop_IT() argument
3494 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop_IT()
3500 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3503 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Stop_IT()
3507 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3510 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Stop_IT()
3514 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3515 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_IT()
3518 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); in HAL_TIM_Encoder_Stop_IT()
3519 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); in HAL_TIM_Encoder_Stop_IT()
3523 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop_IT()
3528 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3529 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3533 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3534 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3535 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3536 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_IT()
3556 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pD… in HAL_TIM_Encoder_Start_DMA() argument
3559 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); in HAL_TIM_Encoder_Start_DMA()
3560 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); in HAL_TIM_Encoder_Start_DMA()
3561 …HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_DMA()
3562 …HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHAN… in HAL_TIM_Encoder_Start_DMA()
3565 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Start_DMA()
3584 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3585 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3609 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3610 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3638 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3639 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3640 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3641 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); in HAL_TIM_Encoder_Start_DMA()
3655 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3656 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3659 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3662 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, in HAL_TIM_Encoder_Start_DMA()
3669 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Start_DMA()
3672 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3675 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3683 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3684 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3687 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; in HAL_TIM_Encoder_Start_DMA()
3689 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, in HAL_TIM_Encoder_Start_DMA()
3696 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Start_DMA()
3699 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3702 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3710 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3711 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3714 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3717 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, in HAL_TIM_Encoder_Start_DMA()
3725 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_Encoder_Start_DMA()
3726 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_Encoder_Start_DMA()
3729 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_Encoder_Start_DMA()
3732 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, in HAL_TIM_Encoder_Start_DMA()
3740 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Start_DMA()
3742 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Start_DMA()
3745 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3746 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); in HAL_TIM_Encoder_Start_DMA()
3749 __HAL_TIM_ENABLE(htim); in HAL_TIM_Encoder_Start_DMA()
3769 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_Encoder_Stop_DMA() argument
3772 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); in HAL_TIM_Encoder_Stop_DMA()
3778 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3781 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Stop_DMA()
3782 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_Encoder_Stop_DMA()
3786 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3789 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Stop_DMA()
3790 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_Encoder_Stop_DMA()
3794 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3795 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); in HAL_TIM_Encoder_Stop_DMA()
3798 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); in HAL_TIM_Encoder_Stop_DMA()
3799 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); in HAL_TIM_Encoder_Stop_DMA()
3800 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_Encoder_Stop_DMA()
3801 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_Encoder_Stop_DMA()
3805 __HAL_TIM_DISABLE(htim); in HAL_TIM_Encoder_Stop_DMA()
3810 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3811 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3815 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3816 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3817 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3818 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in HAL_TIM_Encoder_Stop_DMA()
3846 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) in HAL_TIM_IRQHandler() argument
3848 uint32_t itsource = htim->Instance->DIER; in HAL_TIM_IRQHandler()
3849 uint32_t itflag = htim->Instance->SR; in HAL_TIM_IRQHandler()
3857 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); in HAL_TIM_IRQHandler()
3858 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in HAL_TIM_IRQHandler()
3861 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) in HAL_TIM_IRQHandler()
3864 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3866 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3873 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3874 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3876 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3877 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3880 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3889 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); in HAL_TIM_IRQHandler()
3890 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in HAL_TIM_IRQHandler()
3892 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) in HAL_TIM_IRQHandler()
3895 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3897 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3904 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3905 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3907 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3908 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3911 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3919 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); in HAL_TIM_IRQHandler()
3920 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in HAL_TIM_IRQHandler()
3922 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) in HAL_TIM_IRQHandler()
3925 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3927 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3934 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3935 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3937 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3938 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3941 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3949 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); in HAL_TIM_IRQHandler()
3950 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in HAL_TIM_IRQHandler()
3952 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) in HAL_TIM_IRQHandler()
3955 htim->IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3957 HAL_TIM_IC_CaptureCallback(htim); in HAL_TIM_IRQHandler()
3964 htim->OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3965 htim->PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3967 HAL_TIM_OC_DelayElapsedCallback(htim); in HAL_TIM_IRQHandler()
3968 HAL_TIM_PWM_PulseFinishedCallback(htim); in HAL_TIM_IRQHandler()
3971 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in HAL_TIM_IRQHandler()
3979 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); in HAL_TIM_IRQHandler()
3981 htim->PeriodElapsedCallback(htim); in HAL_TIM_IRQHandler()
3983 HAL_TIM_PeriodElapsedCallback(htim); in HAL_TIM_IRQHandler()
3993 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); in HAL_TIM_IRQHandler()
3995 htim->BreakCallback(htim); in HAL_TIM_IRQHandler()
3997 HAL_TIMEx_BreakCallback(htim); in HAL_TIM_IRQHandler()
4006 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); in HAL_TIM_IRQHandler()
4008 htim->Break2Callback(htim); in HAL_TIM_IRQHandler()
4010 HAL_TIMEx_Break2Callback(htim); in HAL_TIM_IRQHandler()
4019 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); in HAL_TIM_IRQHandler()
4021 htim->TriggerCallback(htim); in HAL_TIM_IRQHandler()
4023 HAL_TIM_TriggerCallback(htim); in HAL_TIM_IRQHandler()
4032 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); in HAL_TIM_IRQHandler()
4034 htim->CommutationCallback(htim); in HAL_TIM_IRQHandler()
4036 HAL_TIMEx_CommutCallback(htim); in HAL_TIM_IRQHandler()
4045 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); in HAL_TIM_IRQHandler()
4047 htim->EncoderIndexCallback(htim); in HAL_TIM_IRQHandler()
4049 HAL_TIMEx_EncoderIndexCallback(htim); in HAL_TIM_IRQHandler()
4058 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); in HAL_TIM_IRQHandler()
4060 htim->DirectionChangeCallback(htim); in HAL_TIM_IRQHandler()
4062 HAL_TIMEx_DirectionChangeCallback(htim); in HAL_TIM_IRQHandler()
4071 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); in HAL_TIM_IRQHandler()
4073 htim->IndexErrorCallback(htim); in HAL_TIM_IRQHandler()
4075 HAL_TIMEx_IndexErrorCallback(htim); in HAL_TIM_IRQHandler()
4084 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); in HAL_TIM_IRQHandler()
4086 htim->TransitionErrorCallback(htim); in HAL_TIM_IRQHandler()
4088 HAL_TIMEx_TransitionErrorCallback(htim); in HAL_TIM_IRQHandler()
4132 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, in HAL_TIM_OC_ConfigChannel() argument
4144 __HAL_LOCK(htim); in HAL_TIM_OC_ConfigChannel()
4151 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4154 TIM_OC1_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4161 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4164 TIM_OC2_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4171 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4174 TIM_OC3_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4181 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4184 TIM_OC4_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4191 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4194 TIM_OC5_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4201 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); in HAL_TIM_OC_ConfigChannel()
4204 TIM_OC6_SetConfig(htim->Instance, sConfig); in HAL_TIM_OC_ConfigChannel()
4213 __HAL_UNLOCK(htim); in HAL_TIM_OC_ConfigChannel()
4231 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConf… in HAL_TIM_IC_ConfigChannel() argument
4236 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4243 __HAL_LOCK(htim); in HAL_TIM_IC_ConfigChannel()
4248 TIM_TI1_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4254 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; in HAL_TIM_IC_ConfigChannel()
4257 htim->Instance->CCMR1 |= sConfig->ICPrescaler; in HAL_TIM_IC_ConfigChannel()
4262 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4264 TIM_TI2_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4270 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; in HAL_TIM_IC_ConfigChannel()
4273 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); in HAL_TIM_IC_ConfigChannel()
4278 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4280 TIM_TI3_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4286 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; in HAL_TIM_IC_ConfigChannel()
4289 htim->Instance->CCMR2 |= sConfig->ICPrescaler; in HAL_TIM_IC_ConfigChannel()
4294 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_IC_ConfigChannel()
4296 TIM_TI4_SetConfig(htim->Instance, in HAL_TIM_IC_ConfigChannel()
4302 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; in HAL_TIM_IC_ConfigChannel()
4305 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); in HAL_TIM_IC_ConfigChannel()
4312 __HAL_UNLOCK(htim); in HAL_TIM_IC_ConfigChannel()
4332 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, in HAL_TIM_PWM_ConfigChannel() argument
4345 __HAL_LOCK(htim); in HAL_TIM_PWM_ConfigChannel()
4352 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4355 TIM_OC1_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4358 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; in HAL_TIM_PWM_ConfigChannel()
4361 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; in HAL_TIM_PWM_ConfigChannel()
4362 htim->Instance->CCMR1 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4369 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4372 TIM_OC2_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4375 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; in HAL_TIM_PWM_ConfigChannel()
4378 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; in HAL_TIM_PWM_ConfigChannel()
4379 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4386 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4389 TIM_OC3_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4392 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; in HAL_TIM_PWM_ConfigChannel()
4395 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; in HAL_TIM_PWM_ConfigChannel()
4396 htim->Instance->CCMR2 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4403 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4406 TIM_OC4_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4409 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; in HAL_TIM_PWM_ConfigChannel()
4412 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; in HAL_TIM_PWM_ConfigChannel()
4413 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4420 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4423 TIM_OC5_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4426 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; in HAL_TIM_PWM_ConfigChannel()
4429 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; in HAL_TIM_PWM_ConfigChannel()
4430 htim->Instance->CCMR3 |= sConfig->OCFastMode; in HAL_TIM_PWM_ConfigChannel()
4437 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); in HAL_TIM_PWM_ConfigChannel()
4440 TIM_OC6_SetConfig(htim->Instance, sConfig); in HAL_TIM_PWM_ConfigChannel()
4443 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; in HAL_TIM_PWM_ConfigChannel()
4446 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; in HAL_TIM_PWM_ConfigChannel()
4447 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; in HAL_TIM_PWM_ConfigChannel()
4456 __HAL_UNLOCK(htim); in HAL_TIM_PWM_ConfigChannel()
4480 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef… in HAL_TIM_OnePulse_ConfigChannel() argument
4493 __HAL_LOCK(htim); in HAL_TIM_OnePulse_ConfigChannel()
4495 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_OnePulse_ConfigChannel()
4509 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4511 TIM_OC1_SetConfig(htim->Instance, &temp1); in HAL_TIM_OnePulse_ConfigChannel()
4517 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4519 TIM_OC2_SetConfig(htim->Instance, &temp1); in HAL_TIM_OnePulse_ConfigChannel()
4534 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4536 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, in HAL_TIM_OnePulse_ConfigChannel()
4540 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; in HAL_TIM_OnePulse_ConfigChannel()
4543 htim->Instance->SMCR &= ~TIM_SMCR_TS; in HAL_TIM_OnePulse_ConfigChannel()
4544 htim->Instance->SMCR |= TIM_TS_TI1FP1; in HAL_TIM_OnePulse_ConfigChannel()
4547 htim->Instance->SMCR &= ~TIM_SMCR_SMS; in HAL_TIM_OnePulse_ConfigChannel()
4548 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; in HAL_TIM_OnePulse_ConfigChannel()
4554 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_OnePulse_ConfigChannel()
4556 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, in HAL_TIM_OnePulse_ConfigChannel()
4560 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; in HAL_TIM_OnePulse_ConfigChannel()
4563 htim->Instance->SMCR &= ~TIM_SMCR_TS; in HAL_TIM_OnePulse_ConfigChannel()
4564 htim->Instance->SMCR |= TIM_TS_TI2FP2; in HAL_TIM_OnePulse_ConfigChannel()
4567 htim->Instance->SMCR &= ~TIM_SMCR_SMS; in HAL_TIM_OnePulse_ConfigChannel()
4568 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; in HAL_TIM_OnePulse_ConfigChannel()
4578 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_OnePulse_ConfigChannel()
4580 __HAL_UNLOCK(htim); in HAL_TIM_OnePulse_ConfigChannel()
4637 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, in HAL_TIM_DMABurst_WriteStart() argument
4643 …status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bu… in HAL_TIM_DMABurst_WriteStart()
4699 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddre… in HAL_TIM_DMABurst_MultiWriteStart() argument
4706 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurst_MultiWriteStart()
4712 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) in HAL_TIM_DMABurst_MultiWriteStart()
4716 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) in HAL_TIM_DMABurst_MultiWriteStart()
4724 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; in HAL_TIM_DMABurst_MultiWriteStart()
4737 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4738 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4741 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4744 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4745 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4755 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4756 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4759 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4762 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4763 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4773 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4774 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4777 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4780 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4781 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4791 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4792 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4795 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4798 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4799 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4809 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4810 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4813 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4816 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4817 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4827 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4828 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4831 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4834 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4835 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4845 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4846 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; in HAL_TIM_DMABurst_MultiWriteStart()
4849 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiWriteStart()
4852 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, in HAL_TIM_DMABurst_MultiWriteStart()
4853 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) in HAL_TIM_DMABurst_MultiWriteStart()
4868 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_MultiWriteStart()
4870 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_MultiWriteStart()
4883 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) in HAL_TIM_DMABurst_WriteStop() argument
4895 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_DMABurst_WriteStop()
4900 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_DMABurst_WriteStop()
4905 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_DMABurst_WriteStop()
4910 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_DMABurst_WriteStop()
4915 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_DMABurst_WriteStop()
4920 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); in HAL_TIM_DMABurst_WriteStop()
4925 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); in HAL_TIM_DMABurst_WriteStop()
4936 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_WriteStop()
4939 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_DMABurst_WriteStop()
4993 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, in HAL_TIM_DMABurst_ReadStart() argument
4998 …status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, Bur… in HAL_TIM_DMABurst_ReadStart()
5053 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddres… in HAL_TIM_DMABurst_MultiReadStart() argument
5060 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurst_MultiReadStart()
5066 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) in HAL_TIM_DMABurst_MultiReadStart()
5070 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) in HAL_TIM_DMABurst_MultiReadStart()
5078 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; in HAL_TIM_DMABurst_MultiReadStart()
5090 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; in HAL_TIM_DMABurst_MultiReadStart()
5091 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5094 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5097 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bur… in HAL_TIM_DMABurst_MultiReadStart()
5108 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5109 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5112 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5115 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5126 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5127 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5130 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5133 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5144 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5145 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5148 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5151 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5162 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; in HAL_TIM_DMABurst_MultiReadStart()
5163 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5166 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5169 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstB… in HAL_TIM_DMABurst_MultiReadStart()
5180 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; in HAL_TIM_DMABurst_MultiReadStart()
5181 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5184 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5187 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_… in HAL_TIM_DMABurst_MultiReadStart()
5198 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; in HAL_TIM_DMABurst_MultiReadStart()
5199 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; in HAL_TIM_DMABurst_MultiReadStart()
5202 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; in HAL_TIM_DMABurst_MultiReadStart()
5205 …if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)Bu… in HAL_TIM_DMABurst_MultiReadStart()
5221 htim->Instance->DCR = (BurstBaseAddress | BurstLength); in HAL_TIM_DMABurst_MultiReadStart()
5224 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_MultiReadStart()
5237 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) in HAL_TIM_DMABurst_ReadStop() argument
5249 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); in HAL_TIM_DMABurst_ReadStop()
5254 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); in HAL_TIM_DMABurst_ReadStop()
5259 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); in HAL_TIM_DMABurst_ReadStop()
5264 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); in HAL_TIM_DMABurst_ReadStop()
5269 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); in HAL_TIM_DMABurst_ReadStop()
5274 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); in HAL_TIM_DMABurst_ReadStop()
5279 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); in HAL_TIM_DMABurst_ReadStop()
5290 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); in HAL_TIM_DMABurst_ReadStop()
5293 htim->DMABurstState = HAL_DMA_BURST_STATE_READY; in HAL_TIM_DMABurst_ReadStop()
5321 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) in HAL_TIM_GenerateEvent() argument
5324 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_GenerateEvent()
5328 __HAL_LOCK(htim); in HAL_TIM_GenerateEvent()
5331 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_GenerateEvent()
5334 htim->Instance->EGR = EventSource; in HAL_TIM_GenerateEvent()
5337 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_GenerateEvent()
5339 __HAL_UNLOCK(htim); in HAL_TIM_GenerateEvent()
5360 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, in HAL_TIM_ConfigOCrefClear() argument
5367 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); in HAL_TIM_ConfigOCrefClear()
5371 __HAL_LOCK(htim); in HAL_TIM_ConfigOCrefClear()
5373 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_ConfigOCrefClear()
5380 if (IS_TIM_OCCS_INSTANCE(htim->Instance)) in HAL_TIM_ConfigOCrefClear()
5382 …CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM… in HAL_TIM_ConfigOCrefClear()
5385 CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL); in HAL_TIM_ConfigOCrefClear()
5389 … CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); in HAL_TIM_ConfigOCrefClear()
5408 if (IS_TIM_OCCS_INSTANCE(htim->Instance)) in HAL_TIM_ConfigOCrefClear()
5411 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); in HAL_TIM_ConfigOCrefClear()
5415 MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); in HAL_TIM_ConfigOCrefClear()
5429 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigOCrefClear()
5430 __HAL_UNLOCK(htim); in HAL_TIM_ConfigOCrefClear()
5434 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigOCrefClear()
5439 if (IS_TIM_OCCS_INSTANCE(htim->Instance)) in HAL_TIM_ConfigOCrefClear()
5442 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); in HAL_TIM_ConfigOCrefClear()
5445 CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL); in HAL_TIM_ConfigOCrefClear()
5464 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); in HAL_TIM_ConfigOCrefClear()
5469 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); in HAL_TIM_ConfigOCrefClear()
5478 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); in HAL_TIM_ConfigOCrefClear()
5483 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); in HAL_TIM_ConfigOCrefClear()
5492 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); in HAL_TIM_ConfigOCrefClear()
5497 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); in HAL_TIM_ConfigOCrefClear()
5506 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); in HAL_TIM_ConfigOCrefClear()
5511 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); in HAL_TIM_ConfigOCrefClear()
5520 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); in HAL_TIM_ConfigOCrefClear()
5525 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); in HAL_TIM_ConfigOCrefClear()
5534 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); in HAL_TIM_ConfigOCrefClear()
5539 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); in HAL_TIM_ConfigOCrefClear()
5548 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigOCrefClear()
5550 __HAL_UNLOCK(htim); in HAL_TIM_ConfigOCrefClear()
5562 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *… in HAL_TIM_ConfigClockSource() argument
5568 __HAL_LOCK(htim); in HAL_TIM_ConfigClockSource()
5570 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_ConfigClockSource()
5576 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_ConfigClockSource()
5579 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_ConfigClockSource()
5585 assert_param(IS_TIM_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5592 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5600 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigClockSource()
5606 tmpsmcr = htim->Instance->SMCR; in HAL_TIM_ConfigClockSource()
5609 htim->Instance->SMCR = tmpsmcr; in HAL_TIM_ConfigClockSource()
5616 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5624 TIM_ETR_SetConfig(htim->Instance, in HAL_TIM_ConfigClockSource()
5629 htim->Instance->SMCR |= TIM_SMCR_ECE; in HAL_TIM_ConfigClockSource()
5636 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5642 TIM_TI1_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5645 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); in HAL_TIM_ConfigClockSource()
5652 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5658 TIM_TI2_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5661 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); in HAL_TIM_ConfigClockSource()
5668 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); in HAL_TIM_ConfigClockSource()
5674 TIM_TI1_ConfigInputStage(htim->Instance, in HAL_TIM_ConfigClockSource()
5677 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); in HAL_TIM_ConfigClockSource()
5701 assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); in HAL_TIM_ConfigClockSource()
5703 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); in HAL_TIM_ConfigClockSource()
5711 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_ConfigClockSource()
5713 __HAL_UNLOCK(htim); in HAL_TIM_ConfigClockSource()
5730 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) in HAL_TIM_ConfigTI1Input() argument
5735 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); in HAL_TIM_ConfigTI1Input()
5739 tmpcr2 = htim->Instance->CR2; in HAL_TIM_ConfigTI1Input()
5748 htim->Instance->CR2 = tmpcr2; in HAL_TIM_ConfigTI1Input()
5762 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef … in HAL_TIM_SlaveConfigSynchro() argument
5765 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); in HAL_TIM_SlaveConfigSynchro()
5767 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); in HAL_TIM_SlaveConfigSynchro()
5769 __HAL_LOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5771 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_SlaveConfigSynchro()
5773 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) in HAL_TIM_SlaveConfigSynchro()
5775 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro()
5776 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5781 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); in HAL_TIM_SlaveConfigSynchro()
5784 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); in HAL_TIM_SlaveConfigSynchro()
5786 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro()
5788 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro()
5802 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, in HAL_TIM_SlaveConfigSynchro_IT() argument
5806 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); in HAL_TIM_SlaveConfigSynchro_IT()
5808 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); in HAL_TIM_SlaveConfigSynchro_IT()
5810 __HAL_LOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5812 htim->State = HAL_TIM_STATE_BUSY; in HAL_TIM_SlaveConfigSynchro_IT()
5814 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) in HAL_TIM_SlaveConfigSynchro_IT()
5816 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro_IT()
5817 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5822 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); in HAL_TIM_SlaveConfigSynchro_IT()
5825 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); in HAL_TIM_SlaveConfigSynchro_IT()
5827 htim->State = HAL_TIM_STATE_READY; in HAL_TIM_SlaveConfigSynchro_IT()
5829 __HAL_UNLOCK(htim); in HAL_TIM_SlaveConfigSynchro_IT()
5845 uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) in HAL_TIM_ReadCapturedValue() argument
5854 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5857 tmpreg = htim->Instance->CCR1; in HAL_TIM_ReadCapturedValue()
5864 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5867 tmpreg = htim->Instance->CCR2; in HAL_TIM_ReadCapturedValue()
5875 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5878 tmpreg = htim->Instance->CCR3; in HAL_TIM_ReadCapturedValue()
5886 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); in HAL_TIM_ReadCapturedValue()
5889 tmpreg = htim->Instance->CCR4; in HAL_TIM_ReadCapturedValue()
5933 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PeriodElapsedCallback() argument
5936 UNUSED(htim); in HAL_TIM_PeriodElapsedCallback()
5948 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PeriodElapsedHalfCpltCallback() argument
5951 UNUSED(htim); in HAL_TIM_PeriodElapsedHalfCpltCallback()
5963 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_OC_DelayElapsedCallback() argument
5966 UNUSED(htim); in HAL_TIM_OC_DelayElapsedCallback()
5978 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) in HAL_TIM_IC_CaptureCallback() argument
5981 UNUSED(htim); in HAL_TIM_IC_CaptureCallback()
5993 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_IC_CaptureHalfCpltCallback() argument
5996 UNUSED(htim); in HAL_TIM_IC_CaptureHalfCpltCallback()
6008 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_PulseFinishedCallback() argument
6011 UNUSED(htim); in HAL_TIM_PWM_PulseFinishedCallback()
6023 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_PWM_PulseFinishedHalfCpltCallback() argument
6026 UNUSED(htim); in HAL_TIM_PWM_PulseFinishedHalfCpltCallback()
6038 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) in HAL_TIM_TriggerCallback() argument
6041 UNUSED(htim); in HAL_TIM_TriggerCallback()
6053 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) in HAL_TIM_TriggerHalfCpltCallback() argument
6056 UNUSED(htim); in HAL_TIM_TriggerHalfCpltCallback()
6068 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) in HAL_TIM_ErrorCallback() argument
6071 UNUSED(htim); in HAL_TIM_ErrorCallback()
6119 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Callb… in HAL_TIM_RegisterCallback() argument
6129 if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_RegisterCallback()
6134 htim->Base_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6138 htim->Base_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6142 htim->IC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6146 htim->IC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6150 htim->OC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6154 htim->OC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6158 htim->PWM_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6162 htim->PWM_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6166 htim->OnePulse_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6170 htim->OnePulse_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6174 htim->Encoder_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6178 htim->Encoder_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6182 htim->HallSensor_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6186 htim->HallSensor_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6190 htim->PeriodElapsedCallback = pCallback; in HAL_TIM_RegisterCallback()
6194 htim->PeriodElapsedHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6198 htim->TriggerCallback = pCallback; in HAL_TIM_RegisterCallback()
6202 htim->TriggerHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6206 htim->IC_CaptureCallback = pCallback; in HAL_TIM_RegisterCallback()
6210 htim->IC_CaptureHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6214 htim->OC_DelayElapsedCallback = pCallback; in HAL_TIM_RegisterCallback()
6218 htim->PWM_PulseFinishedCallback = pCallback; in HAL_TIM_RegisterCallback()
6222 htim->PWM_PulseFinishedHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6226 htim->ErrorCallback = pCallback; in HAL_TIM_RegisterCallback()
6230 htim->CommutationCallback = pCallback; in HAL_TIM_RegisterCallback()
6234 htim->CommutationHalfCpltCallback = pCallback; in HAL_TIM_RegisterCallback()
6238 htim->BreakCallback = pCallback; in HAL_TIM_RegisterCallback()
6242 htim->Break2Callback = pCallback; in HAL_TIM_RegisterCallback()
6246 htim->EncoderIndexCallback = pCallback; in HAL_TIM_RegisterCallback()
6250 htim->DirectionChangeCallback = pCallback; in HAL_TIM_RegisterCallback()
6254 htim->IndexErrorCallback = pCallback; in HAL_TIM_RegisterCallback()
6258 htim->TransitionErrorCallback = pCallback; in HAL_TIM_RegisterCallback()
6267 else if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_RegisterCallback()
6272 htim->Base_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6276 htim->Base_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6280 htim->IC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6284 htim->IC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6288 htim->OC_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6292 htim->OC_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6296 htim->PWM_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6300 htim->PWM_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6304 htim->OnePulse_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6308 htim->OnePulse_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6312 htim->Encoder_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6316 htim->Encoder_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6320 htim->HallSensor_MspInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6324 htim->HallSensor_MspDeInitCallback = pCallback; in HAL_TIM_RegisterCallback()
6382 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef Cal… in HAL_TIM_UnRegisterCallback() argument
6386 if (htim->State == HAL_TIM_STATE_READY) in HAL_TIM_UnRegisterCallback()
6392 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_UnRegisterCallback()
6397 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_UnRegisterCallback()
6402 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_UnRegisterCallback()
6407 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6412 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_UnRegisterCallback()
6417 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6422 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_UnRegisterCallback()
6427 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_UnRegisterCallback()
6432 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_UnRegisterCallback()
6437 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_UnRegisterCallback()
6442 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_UnRegisterCallback()
6447 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_UnRegisterCallback()
6452 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; in HAL_TIM_UnRegisterCallback()
6457 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; in HAL_TIM_UnRegisterCallback()
6462 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; in HAL_TIM_UnRegisterCallback()
6467 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6472 htim->TriggerCallback = HAL_TIM_TriggerCallback; in HAL_TIM_UnRegisterCallback()
6477 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6482 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; in HAL_TIM_UnRegisterCallback()
6487 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6492 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; in HAL_TIM_UnRegisterCallback()
6497 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; in HAL_TIM_UnRegisterCallback()
6502 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6507 htim->ErrorCallback = HAL_TIM_ErrorCallback; in HAL_TIM_UnRegisterCallback()
6512 htim->CommutationCallback = HAL_TIMEx_CommutCallback; in HAL_TIM_UnRegisterCallback()
6517 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; in HAL_TIM_UnRegisterCallback()
6522 htim->BreakCallback = HAL_TIMEx_BreakCallback; in HAL_TIM_UnRegisterCallback()
6527 htim->Break2Callback = HAL_TIMEx_Break2Callback; in HAL_TIM_UnRegisterCallback()
6532 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; in HAL_TIM_UnRegisterCallback()
6537 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; in HAL_TIM_UnRegisterCallback()
6542 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; in HAL_TIM_UnRegisterCallback()
6547 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; in HAL_TIM_UnRegisterCallback()
6556 else if (htim->State == HAL_TIM_STATE_RESET) in HAL_TIM_UnRegisterCallback()
6562 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; in HAL_TIM_UnRegisterCallback()
6567 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; in HAL_TIM_UnRegisterCallback()
6572 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; in HAL_TIM_UnRegisterCallback()
6577 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6582 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; in HAL_TIM_UnRegisterCallback()
6587 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; in HAL_TIM_UnRegisterCallback()
6592 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; in HAL_TIM_UnRegisterCallback()
6597 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; in HAL_TIM_UnRegisterCallback()
6602 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; in HAL_TIM_UnRegisterCallback()
6607 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; in HAL_TIM_UnRegisterCallback()
6612 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; in HAL_TIM_UnRegisterCallback()
6617 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; in HAL_TIM_UnRegisterCallback()
6622 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; in HAL_TIM_UnRegisterCallback()
6627 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; in HAL_TIM_UnRegisterCallback()
6670 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_Base_GetState() argument
6672 return htim->State; in HAL_TIM_Base_GetState()
6680 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_OC_GetState() argument
6682 return htim->State; in HAL_TIM_OC_GetState()
6690 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_PWM_GetState() argument
6692 return htim->State; in HAL_TIM_PWM_GetState()
6700 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_IC_GetState() argument
6702 return htim->State; in HAL_TIM_IC_GetState()
6710 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_OnePulse_GetState() argument
6712 return htim->State; in HAL_TIM_OnePulse_GetState()
6720 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) in HAL_TIM_Encoder_GetState() argument
6722 return htim->State; in HAL_TIM_Encoder_GetState()
6730 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) in HAL_TIM_GetActiveChannel() argument
6732 return htim->Channel; in HAL_TIM_GetActiveChannel()
6748 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channe… in HAL_TIM_GetChannelState() argument
6753 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); in HAL_TIM_GetChannelState()
6755 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); in HAL_TIM_GetChannelState()
6765 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) in HAL_TIM_DMABurstState() argument
6768 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); in HAL_TIM_DMABurstState()
6770 return htim->DMABurstState; in HAL_TIM_DMABurstState()
6792 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAError() local
6794 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMAError()
6796 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMAError()
6797 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6799 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMAError()
6801 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMAError()
6802 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6804 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMAError()
6806 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMAError()
6807 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6809 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMAError()
6811 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMAError()
6812 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMAError()
6816 htim->State = HAL_TIM_STATE_READY; in TIM_DMAError()
6820 htim->ErrorCallback(htim); in TIM_DMAError()
6822 HAL_TIM_ErrorCallback(htim); in TIM_DMAError()
6825 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMAError()
6835 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMADelayPulseCplt() local
6837 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMADelayPulseCplt()
6839 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMADelayPulseCplt()
6843 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6846 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMADelayPulseCplt()
6848 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMADelayPulseCplt()
6852 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6855 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMADelayPulseCplt()
6857 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMADelayPulseCplt()
6861 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6864 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMADelayPulseCplt()
6866 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMADelayPulseCplt()
6870 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMADelayPulseCplt()
6879 htim->PWM_PulseFinishedCallback(htim); in TIM_DMADelayPulseCplt()
6881 HAL_TIM_PWM_PulseFinishedCallback(htim); in TIM_DMADelayPulseCplt()
6884 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMADelayPulseCplt()
6894 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMADelayPulseHalfCplt() local
6896 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMADelayPulseHalfCplt()
6898 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMADelayPulseHalfCplt()
6900 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMADelayPulseHalfCplt()
6902 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMADelayPulseHalfCplt()
6904 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMADelayPulseHalfCplt()
6906 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMADelayPulseHalfCplt()
6908 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMADelayPulseHalfCplt()
6910 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMADelayPulseHalfCplt()
6918 htim->PWM_PulseFinishedHalfCpltCallback(htim); in TIM_DMADelayPulseHalfCplt()
6920 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); in TIM_DMADelayPulseHalfCplt()
6923 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMADelayPulseHalfCplt()
6933 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMACaptureCplt() local
6935 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMACaptureCplt()
6937 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMACaptureCplt()
6941 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6942 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6945 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMACaptureCplt()
6947 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMACaptureCplt()
6951 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6952 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6955 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMACaptureCplt()
6957 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMACaptureCplt()
6961 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6962 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6965 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMACaptureCplt()
6967 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMACaptureCplt()
6971 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6972 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); in TIM_DMACaptureCplt()
6981 htim->IC_CaptureCallback(htim); in TIM_DMACaptureCplt()
6983 HAL_TIM_IC_CaptureCallback(htim); in TIM_DMACaptureCplt()
6986 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMACaptureCplt()
6996 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMACaptureHalfCplt() local
6998 if (hdma == htim->hdma[TIM_DMA_ID_CC1]) in TIM_DMACaptureHalfCplt()
7000 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; in TIM_DMACaptureHalfCplt()
7002 else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) in TIM_DMACaptureHalfCplt()
7004 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; in TIM_DMACaptureHalfCplt()
7006 else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) in TIM_DMACaptureHalfCplt()
7008 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; in TIM_DMACaptureHalfCplt()
7010 else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) in TIM_DMACaptureHalfCplt()
7012 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; in TIM_DMACaptureHalfCplt()
7020 htim->IC_CaptureHalfCpltCallback(htim); in TIM_DMACaptureHalfCplt()
7022 HAL_TIM_IC_CaptureHalfCpltCallback(htim); in TIM_DMACaptureHalfCplt()
7025 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; in TIM_DMACaptureHalfCplt()
7035 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAPeriodElapsedCplt() local
7037 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL) in TIM_DMAPeriodElapsedCplt()
7039 htim->State = HAL_TIM_STATE_READY; in TIM_DMAPeriodElapsedCplt()
7043 htim->PeriodElapsedCallback(htim); in TIM_DMAPeriodElapsedCplt()
7045 HAL_TIM_PeriodElapsedCallback(htim); in TIM_DMAPeriodElapsedCplt()
7056 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMAPeriodElapsedHalfCplt() local
7059 htim->PeriodElapsedHalfCpltCallback(htim); in TIM_DMAPeriodElapsedHalfCplt()
7061 HAL_TIM_PeriodElapsedHalfCpltCallback(htim); in TIM_DMAPeriodElapsedHalfCplt()
7072 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMATriggerCplt() local
7074 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL) in TIM_DMATriggerCplt()
7076 htim->State = HAL_TIM_STATE_READY; in TIM_DMATriggerCplt()
7080 htim->TriggerCallback(htim); in TIM_DMATriggerCplt()
7082 HAL_TIM_TriggerCallback(htim); in TIM_DMATriggerCplt()
7093 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; in TIM_DMATriggerHalfCplt() local
7096 htim->TriggerHalfCpltCallback(htim); in TIM_DMATriggerHalfCplt()
7098 HAL_TIM_TriggerHalfCpltCallback(htim); in TIM_DMATriggerHalfCplt()
7577 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, in TIM_SlaveTimer_SetConfig() argument
7586 tmpsmcr = htim->Instance->SMCR; in TIM_SlaveTimer_SetConfig()
7599 htim->Instance->SMCR = tmpsmcr; in TIM_SlaveTimer_SetConfig()
7607 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7612 TIM_ETR_SetConfig(htim->Instance, in TIM_SlaveTimer_SetConfig()
7622 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7632 tmpccer = htim->Instance->CCER; in TIM_SlaveTimer_SetConfig()
7633 htim->Instance->CCER &= ~TIM_CCER_CC1E; in TIM_SlaveTimer_SetConfig()
7634 tmpccmr1 = htim->Instance->CCMR1; in TIM_SlaveTimer_SetConfig()
7641 htim->Instance->CCMR1 = tmpccmr1; in TIM_SlaveTimer_SetConfig()
7642 htim->Instance->CCER = tmpccer; in TIM_SlaveTimer_SetConfig()
7649 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7654 TIM_TI1_ConfigInputStage(htim->Instance, in TIM_SlaveTimer_SetConfig()
7663 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); in TIM_SlaveTimer_SetConfig()
7668 TIM_TI2_ConfigInputStage(htim->Instance, in TIM_SlaveTimer_SetConfig()
7694 … assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger)); in TIM_SlaveTimer_SetConfig()
8087 void TIM_ResetCallback(TIM_HandleTypeDef *htim) in TIM_ResetCallback() argument
8090 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; in TIM_ResetCallback()
8091 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; in TIM_ResetCallback()
8092 htim->TriggerCallback = HAL_TIM_TriggerCallback; in TIM_ResetCallback()
8093 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; in TIM_ResetCallback()
8094 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; in TIM_ResetCallback()
8095 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; in TIM_ResetCallback()
8096 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; in TIM_ResetCallback()
8097 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; in TIM_ResetCallback()
8098 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; in TIM_ResetCallback()
8099 htim->ErrorCallback = HAL_TIM_ErrorCallback; in TIM_ResetCallback()
8100 htim->CommutationCallback = HAL_TIMEx_CommutCallback; in TIM_ResetCallback()
8101 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; in TIM_ResetCallback()
8102 htim->BreakCallback = HAL_TIMEx_BreakCallback; in TIM_ResetCallback()
8103 htim->Break2Callback = HAL_TIMEx_Break2Callback; in TIM_ResetCallback()
8104 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; in TIM_ResetCallback()
8105 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; in TIM_ResetCallback()
8106 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; in TIM_ResetCallback()
8107 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; in TIM_ResetCallback()