Lines Matching refs:hqspi
260 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, F…
261 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod…
291 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Init() argument
297 if(hqspi == NULL) in HAL_QSPI_Init()
303 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance)); in HAL_QSPI_Init()
304 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); in HAL_QSPI_Init()
305 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
306 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); in HAL_QSPI_Init()
307 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); in HAL_QSPI_Init()
308 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); in HAL_QSPI_Init()
309 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); in HAL_QSPI_Init()
310 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); in HAL_QSPI_Init()
312 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) in HAL_QSPI_Init()
314 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); in HAL_QSPI_Init()
317 if(hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_Init()
320 hqspi->Lock = HAL_UNLOCKED; in HAL_QSPI_Init()
324 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_Init()
325 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_Init()
326 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_Init()
327 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_Init()
328 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_Init()
329 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_Init()
330 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_Init()
331 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_Init()
332 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_Init()
333 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_Init()
335 if(hqspi->MspInitCallback == NULL) in HAL_QSPI_Init()
337 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_Init()
341 hqspi->MspInitCallback(hqspi); in HAL_QSPI_Init()
344 HAL_QSPI_MspInit(hqspi); in HAL_QSPI_Init()
348 HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); in HAL_QSPI_Init()
352 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_Init()
353 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
356 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Init()
361 …MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUAD… in HAL_QSPI_Init()
362 ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | in HAL_QSPI_Init()
363 hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); in HAL_QSPI_Init()
366 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), in HAL_QSPI_Init()
367 ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | in HAL_QSPI_Init()
368 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); in HAL_QSPI_Init()
371 __HAL_QSPI_ENABLE(hqspi); in HAL_QSPI_Init()
374 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Init()
377 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Init()
381 __HAL_UNLOCK(hqspi); in HAL_QSPI_Init()
392 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_DeInit() argument
395 if(hqspi == NULL) in HAL_QSPI_DeInit()
401 __HAL_QSPI_DISABLE(hqspi); in HAL_QSPI_DeInit()
404 if(hqspi->MspDeInitCallback == NULL) in HAL_QSPI_DeInit()
406 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_DeInit()
410 hqspi->MspDeInitCallback(hqspi); in HAL_QSPI_DeInit()
413 HAL_QSPI_MspDeInit(hqspi); in HAL_QSPI_DeInit()
417 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_DeInit()
420 hqspi->State = HAL_QSPI_STATE_RESET; in HAL_QSPI_DeInit()
423 __HAL_UNLOCK(hqspi); in HAL_QSPI_DeInit()
433 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspInit() argument
436 UNUSED(hqspi); in HAL_QSPI_MspInit()
448 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspDeInit() argument
451 UNUSED(hqspi); in HAL_QSPI_MspDeInit()
487 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_IRQHandler() argument
490 uint32_t flag = READ_REG(hqspi->Instance->SR); in HAL_QSPI_IRQHandler()
491 uint32_t itsource = READ_REG(hqspi->Instance->CR); in HAL_QSPI_IRQHandler()
496 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
498 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
501 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
503 if (hqspi->TxXferCount > 0U) in HAL_QSPI_IRQHandler()
506 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_IRQHandler()
507 hqspi->pTxBuffPtr++; in HAL_QSPI_IRQHandler()
508 hqspi->TxXferCount--; in HAL_QSPI_IRQHandler()
514 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
519 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
522 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
524 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
527 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
528 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
529 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
535 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
547 hqspi->FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
549 HAL_QSPI_FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
557 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); in HAL_QSPI_IRQHandler()
560 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
563 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
565 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
568 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
571 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
576 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
580 hqspi->TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
582 HAL_QSPI_TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
585 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
587 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
590 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
593 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
597 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
598 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) in HAL_QSPI_IRQHandler()
600 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
603 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
604 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
605 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
617 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
621 hqspi->RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
623 HAL_QSPI_RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
626 else if(hqspi->State == HAL_QSPI_STATE_BUSY) in HAL_QSPI_IRQHandler()
629 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
633 hqspi->CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
635 HAL_QSPI_CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
638 else if(hqspi->State == HAL_QSPI_STATE_ABORT) in HAL_QSPI_IRQHandler()
641 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_IRQHandler()
644 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
646 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) in HAL_QSPI_IRQHandler()
652 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
654 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
663 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
665 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
679 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); in HAL_QSPI_IRQHandler()
682 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) in HAL_QSPI_IRQHandler()
685 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_IRQHandler()
688 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
693 hqspi->StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
695 HAL_QSPI_StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
703 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); in HAL_QSPI_IRQHandler()
706 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
709 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; in HAL_QSPI_IRQHandler()
711 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
714 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
717 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_IRQHandler()
718 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_IRQHandler()
721 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_IRQHandler()
724 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
728 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
730 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
737 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
741 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
743 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
752 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); in HAL_QSPI_IRQHandler()
756 hqspi->TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
758 HAL_QSPI_TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
776 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Ti… in HAL_QSPI_Command() argument
808 __HAL_LOCK(hqspi); in HAL_QSPI_Command()
810 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command()
812 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command()
815 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command()
818 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_Command()
823 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command()
829 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Command()
833 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Command()
836 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
842 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
852 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command()
865 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) in HAL_QSPI_Command_IT() argument
897 __HAL_LOCK(hqspi); in HAL_QSPI_Command_IT()
899 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command_IT()
901 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command_IT()
904 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command_IT()
907 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Command_IT()
914 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Command_IT()
918 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command_IT()
925 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
928 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); in HAL_QSPI_Command_IT()
933 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command_IT()
936 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
942 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
950 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
965 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Transmit() argument
969 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Transmit()
972 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit()
974 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit()
976 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit()
981 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit()
984 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
985 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
986 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit()
989 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit()
991 while(hqspi->TxXferCount > 0U) in HAL_QSPI_Transmit()
994 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1001 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_Transmit()
1002 hqspi->pTxBuffPtr++; in HAL_QSPI_Transmit()
1003 hqspi->TxXferCount--; in HAL_QSPI_Transmit()
1009 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1014 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Transmit()
1020 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit()
1024 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit()
1034 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit()
1048 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Receive() argument
1052 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive()
1053 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Receive()
1056 __HAL_LOCK(hqspi); in HAL_QSPI_Receive()
1058 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive()
1060 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive()
1065 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive()
1068 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1069 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1070 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive()
1073 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive()
1076 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive()
1078 while(hqspi->RxXferCount > 0U) in HAL_QSPI_Receive()
1081 …status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Time… in HAL_QSPI_Receive()
1088 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_Receive()
1089 hqspi->pRxBuffPtr++; in HAL_QSPI_Receive()
1090 hqspi->RxXferCount--; in HAL_QSPI_Receive()
1096 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Receive()
1101 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Receive()
1107 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive()
1111 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive()
1121 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive()
1133 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_IT() argument
1138 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_IT()
1140 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_IT()
1142 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_IT()
1147 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_IT()
1150 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1151 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1152 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_IT()
1155 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Transmit_IT()
1158 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_IT()
1161 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1164 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Transmit_IT()
1168 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_IT()
1172 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1180 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1193 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_IT() argument
1196 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_IT()
1199 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_IT()
1201 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_IT()
1203 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_IT()
1208 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_IT()
1211 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1212 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1213 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_IT()
1216 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Receive_IT()
1219 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_IT()
1222 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_IT()
1225 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1228 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Receive_IT()
1232 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_IT()
1236 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1244 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1261 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_DMA() argument
1264 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Transmit_DMA()
1267 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1269 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_DMA()
1272 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_DMA()
1277 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Transmit_DMA()
1279 hqspi->TxXferCount = data_size; in HAL_QSPI_Transmit_DMA()
1281 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Transmit_DMA()
1283 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1287 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1291 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1295 hqspi->TxXferCount = (data_size >> 1U); in HAL_QSPI_Transmit_DMA()
1298 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Transmit_DMA()
1300 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1304 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1308 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1312 hqspi->TxXferCount = (data_size >> 2U); in HAL_QSPI_Transmit_DMA()
1323 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_DMA()
1326 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Transmit_DMA()
1329 hqspi->TxXferSize = hqspi->TxXferCount; in HAL_QSPI_Transmit_DMA()
1330 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_DMA()
1333 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_DMA()
1336 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; in HAL_QSPI_Transmit_DMA()
1339 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; in HAL_QSPI_Transmit_DMA()
1342 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Transmit_DMA()
1345 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Transmit_DMA()
1348 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; in HAL_QSPI_Transmit_DMA()
1349 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Transmit_DMA()
1352 …if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSi… in HAL_QSPI_Transmit_DMA()
1355 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1358 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Transmit_DMA()
1361 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Transmit_DMA()
1366 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Transmit_DMA()
1367 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit_DMA()
1370 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1376 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1380 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1388 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1405 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_DMA() argument
1408 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_DMA()
1409 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Receive_DMA()
1412 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_DMA()
1414 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_DMA()
1417 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_DMA()
1422 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Receive_DMA()
1424 hqspi->RxXferCount = data_size; in HAL_QSPI_Receive_DMA()
1426 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Receive_DMA()
1428 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1432 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1436 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1440 hqspi->RxXferCount = (data_size >> 1U); in HAL_QSPI_Receive_DMA()
1443 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Receive_DMA()
1445 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
1449 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1453 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1457 hqspi->RxXferCount = (data_size >> 2U); in HAL_QSPI_Receive_DMA()
1468 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_DMA()
1471 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Receive_DMA()
1474 hqspi->RxXferSize = hqspi->RxXferCount; in HAL_QSPI_Receive_DMA()
1475 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_DMA()
1478 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; in HAL_QSPI_Receive_DMA()
1481 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; in HAL_QSPI_Receive_DMA()
1484 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Receive_DMA()
1487 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Receive_DMA()
1490 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; in HAL_QSPI_Receive_DMA()
1491 MODIFY_REG(hqspi->hdma->Instance->CCR, DMA_CCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Receive_DMA()
1494 …if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSi… in HAL_QSPI_Receive_DMA()
1497 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_DMA()
1500 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_DMA()
1503 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1506 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Receive_DMA()
1509 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Receive_DMA()
1514 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Receive_DMA()
1515 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive_DMA()
1518 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1524 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1528 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1536 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1551 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_Au… in HAL_QSPI_AutoPolling() argument
1587 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling()
1589 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling()
1591 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling()
1594 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling()
1597 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1602 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling()
1605 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling()
1608 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling()
1612 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling()
1617 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling()
1620 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1624 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); in HAL_QSPI_AutoPolling()
1627 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_AutoPolling()
1637 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling()
1651 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI… in HAL_QSPI_AutoPolling_IT() argument
1688 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1690 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling_IT()
1692 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling_IT()
1695 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling_IT()
1698 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_AutoPolling_IT()
1703 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling_IT()
1706 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling_IT()
1709 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling_IT()
1712 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling_IT()
1716 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); in HAL_QSPI_AutoPolling_IT()
1720 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling_IT()
1723 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1726 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_AutoPolling_IT()
1732 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1740 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1755 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_M… in HAL_QSPI_MemoryMapped() argument
1789 __HAL_LOCK(hqspi); in HAL_QSPI_MemoryMapped()
1791 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_MemoryMapped()
1793 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_MemoryMapped()
1796 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; in HAL_QSPI_MemoryMapped()
1799 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_MemoryMapped()
1804 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); in HAL_QSPI_MemoryMapped()
1811 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); in HAL_QSPI_MemoryMapped()
1814 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); in HAL_QSPI_MemoryMapped()
1817 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); in HAL_QSPI_MemoryMapped()
1821 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); in HAL_QSPI_MemoryMapped()
1830 __HAL_UNLOCK(hqspi); in HAL_QSPI_MemoryMapped()
1841 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_ErrorCallback() argument
1844 UNUSED(hqspi); in HAL_QSPI_ErrorCallback()
1856 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_AbortCpltCallback() argument
1859 UNUSED(hqspi); in HAL_QSPI_AbortCpltCallback()
1871 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_CmdCpltCallback() argument
1874 UNUSED(hqspi); in HAL_QSPI_CmdCpltCallback()
1886 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxCpltCallback() argument
1889 UNUSED(hqspi); in HAL_QSPI_RxCpltCallback()
1901 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxCpltCallback() argument
1904 UNUSED(hqspi); in HAL_QSPI_TxCpltCallback()
1916 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxHalfCpltCallback() argument
1919 UNUSED(hqspi); in HAL_QSPI_RxHalfCpltCallback()
1931 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxHalfCpltCallback() argument
1934 UNUSED(hqspi); in HAL_QSPI_TxHalfCpltCallback()
1946 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_FifoThresholdCallback() argument
1949 UNUSED(hqspi); in HAL_QSPI_FifoThresholdCallback()
1961 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_StatusMatchCallback() argument
1964 UNUSED(hqspi); in HAL_QSPI_StatusMatchCallback()
1976 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TimeOutCallback() argument
1979 UNUSED(hqspi); in HAL_QSPI_TimeOutCallback()
2007 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef … in HAL_QSPI_RegisterCallback() argument
2014 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2019 __HAL_LOCK(hqspi); in HAL_QSPI_RegisterCallback()
2021 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_RegisterCallback()
2026 hqspi->ErrorCallback = pCallback; in HAL_QSPI_RegisterCallback()
2029 hqspi->AbortCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2032 hqspi->FifoThresholdCallback = pCallback; in HAL_QSPI_RegisterCallback()
2035 hqspi->CmdCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2038 hqspi->RxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2041 hqspi->TxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2044 hqspi->RxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2047 hqspi->TxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2050 hqspi->StatusMatchCallback = pCallback; in HAL_QSPI_RegisterCallback()
2053 hqspi->TimeOutCallback = pCallback; in HAL_QSPI_RegisterCallback()
2056 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2059 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2063 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2069 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_RegisterCallback()
2074 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2077 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2081 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2090 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2096 __HAL_UNLOCK(hqspi); in HAL_QSPI_RegisterCallback()
2120 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDe… in HAL_QSPI_UnRegisterCallback() argument
2125 __HAL_LOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2127 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_UnRegisterCallback()
2132 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_UnRegisterCallback()
2135 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_UnRegisterCallback()
2138 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_UnRegisterCallback()
2141 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_UnRegisterCallback()
2144 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2147 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2150 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2153 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2156 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_UnRegisterCallback()
2159 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_UnRegisterCallback()
2162 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2165 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2169 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2175 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_UnRegisterCallback()
2180 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2183 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2187 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2196 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2202 __HAL_UNLOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2234 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetState() argument
2237 return hqspi->State; in HAL_QSPI_GetState()
2245 uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetError() argument
2247 return hqspi->ErrorCode; in HAL_QSPI_GetError()
2255 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort() argument
2261 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort()
2264 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort()
2266 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort()
2269 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort()
2272 status = HAL_DMA_Abort(hqspi->hdma); in HAL_QSPI_Abort()
2275 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Abort()
2279 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort()
2282 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort()
2285 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2289 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort()
2292 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2298 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_Abort()
2301 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2307 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2319 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort_IT() argument
2324 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort_IT()
2327 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort_IT()
2330 hqspi->State = HAL_QSPI_STATE_ABORT; in HAL_QSPI_Abort_IT()
2333 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); in HAL_QSPI_Abort_IT()
2335 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort_IT()
2338 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort_IT()
2341 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_Abort_IT()
2342 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_Abort_IT()
2345 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2349 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2351 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2357 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort_IT()
2360 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort_IT()
2363 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in HAL_QSPI_Abort_IT()
2366 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort_IT()
2371 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2383 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) in HAL_QSPI_SetTimeout() argument
2385 hqspi->Timeout = Timeout; in HAL_QSPI_SetTimeout()
2393 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) in HAL_QSPI_SetFifoThreshold() argument
2398 __HAL_LOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2400 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFifoThreshold()
2403 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2406 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_SetFifoThreshold()
2407 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
2415 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2425 uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetFifoThreshold() argument
2427 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); in HAL_QSPI_GetFifoThreshold()
2437 HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) in HAL_QSPI_SetFlashID() argument
2445 __HAL_LOCK(hqspi); in HAL_QSPI_SetFlashID()
2447 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFlashID()
2450 hqspi->Init.FlashID = FlashID; in HAL_QSPI_SetFlashID()
2453 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); in HAL_QSPI_SetFlashID()
2461 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFlashID()
2486 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxCplt() local
2487 hqspi->RxXferCount = 0U; in QSPI_DMARxCplt()
2490 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMARxCplt()
2500 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxCplt() local
2501 hqspi->TxXferCount = 0U; in QSPI_DMATxCplt()
2504 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMATxCplt()
2514 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxHalfCplt() local
2517 hqspi->RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2519 HAL_QSPI_RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2530 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxHalfCplt() local
2533 hqspi->TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2535 HAL_QSPI_TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2546 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAError() local
2548 hqspi->RxXferCount = 0U; in QSPI_DMAError()
2549 hqspi->TxXferCount = 0U; in QSPI_DMAError()
2550 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in QSPI_DMAError()
2553 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in QSPI_DMAError()
2556 (void)HAL_QSPI_Abort_IT(hqspi); in QSPI_DMAError()
2567 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAAbortCplt() local
2569 hqspi->RxXferCount = 0U; in QSPI_DMAAbortCplt()
2570 hqspi->TxXferCount = 0U; in QSPI_DMAAbortCplt()
2572 if(hqspi->State == HAL_QSPI_STATE_ABORT) in QSPI_DMAAbortCplt()
2576 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in QSPI_DMAAbortCplt()
2579 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMAAbortCplt()
2582 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in QSPI_DMAAbortCplt()
2588 hqspi->State = HAL_QSPI_STATE_READY; in QSPI_DMAAbortCplt()
2592 hqspi->ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2594 HAL_QSPI_ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2608 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, in QSPI_WaitFlagStateUntilTimeout() argument
2612 while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) in QSPI_WaitFlagStateUntilTimeout()
2619 hqspi->State = HAL_QSPI_STATE_ERROR; in QSPI_WaitFlagStateUntilTimeout()
2620 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; in QSPI_WaitFlagStateUntilTimeout()
2641 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod… in QSPI_Config() argument
2648 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); in QSPI_Config()
2656 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2662 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2671 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2678 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2685 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()
2694 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2702 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2709 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2715 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()
2724 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2730 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2739 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2746 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2752 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()
2761 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2769 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2778 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2784 CLEAR_REG(hqspi->Instance->AR); in QSPI_Config()