Lines Matching refs:CCER
540 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_ENCODER_Init()
546 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_ENCODER_Init()
573 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_ENCODER_Init()
629 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); in LL_TIM_HALLSENSOR_Init()
638 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in LL_TIM_HALLSENSOR_Init()
679 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in LL_TIM_HALLSENSOR_Init()
810 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); in OC1Config()
813 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC1Config()
863 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC1Config()
889 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); in OC2Config()
892 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC2Config()
942 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC2Config()
968 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); in OC3Config()
971 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC3Config()
1021 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC3Config()
1047 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); in OC4Config()
1050 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC4Config()
1088 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC4Config()
1115 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E); in OC5Config()
1118 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC5Config()
1149 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC5Config()
1176 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E); in OC6Config()
1179 tmpccer = LL_TIM_ReadReg(TIMx, CCER); in OC6Config()
1209 LL_TIM_WriteReg(TIMx, CCER, tmpccer); in OC6Config()
1232 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; in IC1Config()
1240 MODIFY_REG(TIMx->CCER, in IC1Config()
1265 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; in IC2Config()
1273 MODIFY_REG(TIMx->CCER, in IC2Config()
1298 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; in IC3Config()
1306 MODIFY_REG(TIMx->CCER, in IC3Config()
1331 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; in IC4Config()
1339 MODIFY_REG(TIMx->CCER, in IC4Config()