Lines Matching refs:hdma

112 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32…
113 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma);
114 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma);
152 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) in HAL_DMA_Init() argument
155 if (hdma == NULL) in HAL_DMA_Init()
161 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_Init()
162 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); in HAL_DMA_Init()
163 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); in HAL_DMA_Init()
164 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); in HAL_DMA_Init()
165 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); in HAL_DMA_Init()
166 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); in HAL_DMA_Init()
167 assert_param(IS_DMA_MODE(hdma->Init.Mode)); in HAL_DMA_Init()
168 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); in HAL_DMA_Init()
170 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); in HAL_DMA_Init()
174 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) in HAL_DMA_Init()
177hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Chann… in HAL_DMA_Init()
178 hdma->DmaBaseAddress = DMA1; in HAL_DMA_Init()
183hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Chann… in HAL_DMA_Init()
184 hdma->DmaBaseAddress = DMA2; in HAL_DMA_Init()
187hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Chann… in HAL_DMA_Init()
191 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Init()
194 CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ in HAL_DMA_Init()
199 SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ in HAL_DMA_Init()
200 hdma->Init.PeriphInc | hdma->Init.MemInc | \ in HAL_DMA_Init()
201 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | \ in HAL_DMA_Init()
202 hdma->Init.Mode | hdma->Init.Priority)); in HAL_DMA_Init()
207 DMA_CalcDMAMUXChannelBaseAndMask(hdma); in HAL_DMA_Init()
209 if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) in HAL_DMA_Init()
212 hdma->Init.Request = DMA_REQUEST_MEM2MEM; in HAL_DMA_Init()
216 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); in HAL_DMA_Init()
219 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_Init()
221 if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) in HAL_DMA_Init()
226 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); in HAL_DMA_Init()
229 hdma->DMAmuxRequestGen->RGCR = 0U; in HAL_DMA_Init()
232 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_Init()
236 hdma->DMAmuxRequestGen = 0U; in HAL_DMA_Init()
237 hdma->DMAmuxRequestGenStatus = 0U; in HAL_DMA_Init()
238 hdma->DMAmuxRequestGenStatusMask = 0U; in HAL_DMA_Init()
242 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Init()
245 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
248 __HAL_UNLOCK(hdma); in HAL_DMA_Init()
259 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) in HAL_DMA_DeInit() argument
262 if (NULL == hdma) in HAL_DMA_DeInit()
268 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_DeInit()
271 __HAL_DMA_DISABLE(hdma); in HAL_DMA_DeInit()
275 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) in HAL_DMA_DeInit()
278hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Chann… in HAL_DMA_DeInit()
279 hdma->DmaBaseAddress = DMA1; in HAL_DMA_DeInit()
284hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Chann… in HAL_DMA_DeInit()
285 hdma->DmaBaseAddress = DMA2; in HAL_DMA_DeInit()
288hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Chann… in HAL_DMA_DeInit()
292 hdma->Instance->CCR = 0U; in HAL_DMA_DeInit()
296 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); in HAL_DMA_DeInit()
298 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU))); in HAL_DMA_DeInit()
304 DMA_CalcDMAMUXChannelBaseAndMask(hdma); in HAL_DMA_DeInit()
307 hdma->DMAmuxChannel->CCR = 0U; in HAL_DMA_DeInit()
310 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_DeInit()
313 if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) in HAL_DMA_DeInit()
318 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); in HAL_DMA_DeInit()
321 hdma->DMAmuxRequestGen->RGCR = 0U; in HAL_DMA_DeInit()
324 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_DeInit()
327 hdma->DMAmuxRequestGen = 0U; in HAL_DMA_DeInit()
328 hdma->DMAmuxRequestGenStatus = 0U; in HAL_DMA_DeInit()
329 hdma->DMAmuxRequestGenStatusMask = 0U; in HAL_DMA_DeInit()
332 hdma->XferCpltCallback = NULL; in HAL_DMA_DeInit()
333 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_DeInit()
334 hdma->XferErrorCallback = NULL; in HAL_DMA_DeInit()
335 hdma->XferAbortCallback = NULL; in HAL_DMA_DeInit()
338 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_DeInit()
341 hdma->State = HAL_DMA_STATE_RESET; in HAL_DMA_DeInit()
344 __HAL_UNLOCK(hdma); in HAL_DMA_DeInit()
382 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, … in HAL_DMA_Start() argument
390 __HAL_LOCK(hdma); in HAL_DMA_Start()
392 if (hdma->State == HAL_DMA_STATE_READY) in HAL_DMA_Start()
395 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start()
398 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start()
401 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Start()
404 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start()
407 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start()
412 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; in HAL_DMA_Start()
415 __HAL_UNLOCK(hdma); in HAL_DMA_Start()
433 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres… in HAL_DMA_Start_IT() argument
442 __HAL_LOCK(hdma); in HAL_DMA_Start_IT()
444 if (hdma->State == HAL_DMA_STATE_READY) in HAL_DMA_Start_IT()
447 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start_IT()
448 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start_IT()
451 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Start_IT()
454 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start_IT()
458 if (NULL != hdma->XferHalfCpltCallback) in HAL_DMA_Start_IT()
461 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); in HAL_DMA_Start_IT()
465 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); in HAL_DMA_Start_IT()
466 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); in HAL_DMA_Start_IT()
470 if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) in HAL_DMA_Start_IT()
473 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; in HAL_DMA_Start_IT()
476 if (hdma->DMAmuxRequestGen != 0U) in HAL_DMA_Start_IT()
480 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; in HAL_DMA_Start_IT()
484 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start_IT()
489 hdma->ErrorCode = HAL_DMA_ERROR_BUSY; in HAL_DMA_Start_IT()
492 __HAL_UNLOCK(hdma); in HAL_DMA_Start_IT()
507 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort() argument
510 if (NULL == hdma) in HAL_DMA_Abort()
516 if (hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort()
518 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort()
521 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
528 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); in HAL_DMA_Abort()
531 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort()
534 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort()
538 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); in HAL_DMA_Abort()
540 __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); in HAL_DMA_Abort()
544 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_Abort()
546 if (hdma->DMAmuxRequestGen != 0U) in HAL_DMA_Abort()
550 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; in HAL_DMA_Abort()
553 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_Abort()
557 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Abort()
560 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
572 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort_IT() argument
576 if (hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort_IT()
579 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort_IT()
586 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); in HAL_DMA_Abort_IT()
589 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort_IT()
592 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; in HAL_DMA_Abort_IT()
596 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); in HAL_DMA_Abort_IT()
598 __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU))); in HAL_DMA_Abort_IT()
602 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; in HAL_DMA_Abort_IT()
604 if (hdma->DMAmuxRequestGen != 0U) in HAL_DMA_Abort_IT()
608 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; in HAL_DMA_Abort_IT()
611 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; in HAL_DMA_Abort_IT()
615 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Abort_IT()
618 __HAL_UNLOCK(hdma); in HAL_DMA_Abort_IT()
621 if (hdma->XferAbortCallback != NULL) in HAL_DMA_Abort_IT()
623 hdma->XferAbortCallback(hdma); in HAL_DMA_Abort_IT()
637 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com… argument
643 if (hdma->State != HAL_DMA_STATE_BUSY)
646 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER;
647 __HAL_UNLOCK(hdma);
652 if ((hdma->Instance->CCR & DMA_CCR_CIRC) != 0U)
654 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
662 temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU);
667 temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU);
674 while ((hdma->DmaBaseAddress->ISR & temp) == 0U)
676 if ((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U)
681 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
684 hdma->ErrorCode = HAL_DMA_ERROR_TE;
687 hdma->State = HAL_DMA_STATE_READY;
690 __HAL_UNLOCK(hdma);
695 while (0U == __HAL_DMA_GET_FLAG(hdma, temp))
697 if (0U != __HAL_DMA_GET_FLAG(hdma, (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))))
702 __HAL_DMA_CLEAR_FLAG(hdma, ((DMA_FLAG_GI1) << (hdma->ChannelIndex & 0x1CU)));
705 hdma->ErrorCode = HAL_DMA_ERROR_TE;
708 hdma->State = HAL_DMA_STATE_READY;
711 __HAL_UNLOCK(hdma);
722 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT;
725 hdma->State = HAL_DMA_STATE_READY;
728 __HAL_UNLOCK(hdma);
736 if (hdma->DMAmuxRequestGen != 0U)
739 if ((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U)
742 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE;
745 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
748 hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN;
753 if ((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U)
756 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
759 hdma->ErrorCode |= HAL_DMA_ERROR_SYNC;
766 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU));
768 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
772 __HAL_UNLOCK(hdma);
776 hdma->State = HAL_DMA_STATE_READY;
782 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU));
784 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
797 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) argument
800 uint32_t flag_it = hdma->DmaBaseAddress->ISR;
804 uint32_t source_it = hdma->Instance->CCR;
807 …if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT)…
810 if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
813 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
817 hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU);
819 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU)));
825 if (hdma->XferHalfCpltCallback != NULL)
828 hdma->XferHalfCpltCallback(hdma);
833 …else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it &…
835 if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
838 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC);
841 hdma->State = HAL_DMA_STATE_READY;
844 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)));
847 __HAL_UNLOCK(hdma);
849 if (hdma->XferCpltCallback != NULL)
852 hdma->XferCpltCallback(hdma);
857 …else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_I…
862 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE));
866 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
868 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
872 hdma->ErrorCode = HAL_DMA_ERROR_TE;
875 hdma->State = HAL_DMA_STATE_READY;
878 __HAL_UNLOCK(hdma);
880 if (hdma->XferErrorCallback != NULL)
883 hdma->XferErrorCallback(hdma);
903 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb… argument
908 __HAL_LOCK(hdma);
910 if (hdma->State == HAL_DMA_STATE_READY)
915 hdma->XferCpltCallback = pCallback;
919 hdma->XferHalfCpltCallback = pCallback;
923 hdma->XferErrorCallback = pCallback;
927 hdma->XferAbortCallback = pCallback;
941 __HAL_UNLOCK(hdma);
954 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal… argument
959 __HAL_LOCK(hdma);
961 if (hdma->State == HAL_DMA_STATE_READY)
966 hdma->XferCpltCallback = NULL;
970 hdma->XferHalfCpltCallback = NULL;
974 hdma->XferErrorCallback = NULL;
978 hdma->XferAbortCallback = NULL;
982 hdma->XferCpltCallback = NULL;
983 hdma->XferHalfCpltCallback = NULL;
984 hdma->XferErrorCallback = NULL;
985 hdma->XferAbortCallback = NULL;
999 __HAL_UNLOCK(hdma);
1032 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) argument
1035 return hdma->State;
1044 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) argument
1047 return hdma->ErrorCode;
1071 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32… argument
1074 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask;
1076 if (hdma->DMAmuxRequestGen != 0U)
1079 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask;
1084 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU));
1086 __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_GI1 << (hdma->ChannelIndex & 0x1CU)));
1090 hdma->Instance->CNDTR = DataLength;
1093 if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
1096 hdma->Instance->CPAR = DstAddress;
1099 hdma->Instance->CMAR = SrcAddress;
1105 hdma->Instance->CPAR = SrcAddress;
1108 hdma->Instance->CMAR = DstAddress;
1118 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) argument
1124 if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
1128 hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
1131 channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
1137 hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
1140 channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U);
1144hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + ((hdma->Ch…
1147 channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
1151 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
1154 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU);
1164 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) argument
1166 uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID;
1169hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenera…
1171 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
1174 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);