Lines Matching refs:PWR
34 #if defined(PWR)
181 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA)))
182 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB)))
183 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC)))
184 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD)))
186 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE)))
188 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF)))
235 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
242 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
270 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); in LL_PWR_SetRegulVoltageScaling()
282 return (READ_BIT(PWR->CR1, PWR_CR1_VOS)); in LL_PWR_GetRegulVoltageScaling()
292 SET_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_EnableLowPowerRunMode()
302 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); in LL_PWR_DisableLowPowerRunMode()
312 return ((READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)) ? 1UL : 0UL); in LL_PWR_IsEnabledLowPowerRunMode()
342 SET_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_EnableBkUpAccess()
352 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); in LL_PWR_DisableBkUpAccess()
362 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); in LL_PWR_IsEnabledBkUpAccess()
372 SET_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP); in LL_PWR_EnableFlashPowerDownInLPSleep()
382 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP); in LL_PWR_DisableFlashPowerDownInLPSleep()
392 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPSLP) == (PWR_CR1_FPD_LPSLP)) ? 1UL : 0UL); in LL_PWR_IsEnableFlashPowerDownInLPSleep()
402 SET_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN); in LL_PWR_EnableFlashPowerDownInLPRun()
412 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN); in LL_PWR_DisableFlashPowerDownInLPRun()
422 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_LPRUN) == (PWR_CR1_FPD_LPRUN)) ? 1UL : 0UL); in LL_PWR_IsEnableFlashPowerDownInLPRun()
432 SET_BIT(PWR->CR1, PWR_CR1_FPD_STOP); in LL_PWR_EnableFlashPowerDownInStop()
442 CLEAR_BIT(PWR->CR1, PWR_CR1_FPD_STOP); in LL_PWR_DisableFlashPowerDownInStop()
452 return ((READ_BIT(PWR->CR1, PWR_CR1_FPD_STOP) == (PWR_CR1_FPD_STOP)) ? 1UL : 0UL); in LL_PWR_IsEnableFlashPowerDownInStop()
463 SET_BIT(PWR->CR2, PWR_CR2_IOSV); in LL_PWR_EnableVddIO2()
473 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); in LL_PWR_DisableVddIO2()
483 return ((READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddIO2()
495 SET_BIT(PWR->CR2, PWR_CR2_USV); in LL_PWR_EnableVddUSB()
505 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); in LL_PWR_DisableVddUSB()
515 return ((READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)) ? 1UL : 0UL); in LL_PWR_IsEnabledVddUSB()
531 SET_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_EnablePVM()
545 CLEAR_BIT(PWR->CR2, PeriphVoltage); in LL_PWR_DisablePVM()
559 return ((READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVM()
575 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); in LL_PWR_SetPowerMode()
589 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); in LL_PWR_GetPowerMode()
609 MODIFY_REG(PWR->CR2, PWR_CR2_PVDRT, PVDHighLevel); in LL_PWR_SetPVDHighLevel()
627 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDRT)); in LL_PWR_GetPVDHighLevel()
644 MODIFY_REG(PWR->CR2, PWR_CR2_PVDFT, PVDLowLevel); in LL_PWR_SetPVDLowLevel()
661 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PVDFT)); in LL_PWR_GetPVDLowLevel()
671 SET_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_EnablePVD()
681 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); in LL_PWR_DisablePVD()
691 return ((READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)) ? 1UL : 0UL); in LL_PWR_IsEnabledPVD()
702 SET_BIT(PWR->CR3, PWR_CR3_EIWUL); in LL_PWR_EnableInternWU()
712 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); in LL_PWR_DisableInternWU()
722 return ((READ_BIT(PWR->CR3, PWR_CR3_EIWUL) == (PWR_CR3_EIWUL)) ? 1UL : 0UL); in LL_PWR_IsEnabledInternWU()
732 SET_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_EnablePUPDCfg()
742 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); in LL_PWR_DisablePUPDCfg()
752 return ((READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)) ? 1UL : 0UL); in LL_PWR_IsEnabledPUPDCfg()
763 SET_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_EnableSRAMRetention()
773 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); in LL_PWR_DisableSRAMRetention()
783 return ((READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)) ? 1UL : 0UL); in LL_PWR_IsEnabledSRAMRetention()
795 SET_BIT(PWR->CR3, PWR_CR3_ENB_ULP); in LL_PWR_EnableLPMUResetSamplingMode()
805 CLEAR_BIT(PWR->CR3, PWR_CR3_ENB_ULP); in LL_PWR_DisableLPMUResetSamplingMode()
815 return ((READ_BIT(PWR->CR3, PWR_CR3_ENB_ULP) == (PWR_CR3_ENB_ULP)) ? 1UL : 0UL); in LL_PWR_IsEnableLPMUResetSamplingMode()
839 SET_BIT(PWR->CR3, WakeUpPin); in LL_PWR_EnableWakeUpPin()
862 CLEAR_BIT(PWR->CR3, WakeUpPin); in LL_PWR_DisableWakeUpPin()
885 return ((READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsEnabledWakeUpPin()
898 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); in LL_PWR_SetBattChargResistor()
910 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); in LL_PWR_GetBattChargResistor()
920 SET_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_EnableBatteryCharging()
930 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); in LL_PWR_DisableBatteryCharging()
940 return ((READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)) ? 1UL : 0UL); in LL_PWR_IsEnabledBatteryCharging()
963 SET_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityLow()
986 CLEAR_BIT(PWR->CR4, WakeUpPin); in LL_PWR_SetWakeUpPinPolarityHigh()
1009 return ((READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); in LL_PWR_IsWakeUpPinPolarityLow()
1261 return ((READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_InternWU()
1271 return ((READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_SB()
1281 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF6) == (PWR_SR1_WUF6)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU6()
1292 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU5()
1303 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU4()
1314 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU3()
1325 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU2()
1335 return ((READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_WU1()
1345 WRITE_REG(PWR->SCR, PWR_SCR_CSBF); in LL_PWR_ClearFlag_SB()
1355 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); in LL_PWR_ClearFlag_WU()
1365 WRITE_REG(PWR->SCR, PWR_SCR_CWUF6); in LL_PWR_ClearFlag_WU6()
1376 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); in LL_PWR_ClearFlag_WU5()
1387 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); in LL_PWR_ClearFlag_WU4()
1398 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); in LL_PWR_ClearFlag_WU3()
1409 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); in LL_PWR_ClearFlag_WU2()
1419 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); in LL_PWR_ClearFlag_WU1()
1431 return ((READ_BIT(PWR->SR2, PWR_SR2_PVMO_USB) == (PWR_SR2_PVMO_USB)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVMOUSB()
1444 return ((READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_PVDO()
1459 return ((READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_VOS()
1472 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPF()
1482 return ((READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_REGLPS()
1492 return ((READ_BIT(PWR->SR2, PWR_SR2_FLASH_RDY) == (PWR_SR2_FLASH_RDY)) ? 1UL : 0UL); in LL_PWR_IsActiveFlag_FLASH_RDY()