2324   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution);  in LL_ADC_SetResolution()
2341   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES));  in LL_ADC_GetResolution()
2360   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment);  in LL_ADC_SetDataAlignment()
2375   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN));  in LL_ADC_GetDataAlignment()
2432   MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode);  in LL_ADC_SetLowPowerMode()
2485   return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF)));  in LL_ADC_GetLowPowerMode()
2659   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource);  in LL_ADC_REG_SetTriggerSource()
2691   __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN);  in LL_ADC_REG_GetTriggerSource()
2718 …return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ?…  in LL_ADC_REG_IsTriggerSourceSWStart()
2737   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge);  in LL_ADC_REG_SetTriggerEdge()
2752   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN));  in LL_ADC_REG_GetTriggerEdge()
2789   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability);  in LL_ADC_REG_SetSequencerConfigurable()
2815   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD));  in LL_ADC_REG_GetSequencerConfigurable()
2995   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection);  in LL_ADC_REG_SetSequencerScanDirection()
3013   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR));  in LL_ADC_REG_GetSequencerScanDirection()
3034   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont);  in LL_ADC_REG_SetSequencerDiscont()
3049   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN));  in LL_ADC_REG_GetSequencerDiscont()
3615   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous);  in LL_ADC_REG_SetContinuousMode()
3632   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT));  in LL_ADC_REG_GetContinuousMode()
3669   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer);  in LL_ADC_REG_SetDMATransfer()
3702   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG));  in LL_ADC_REG_GetDMATransfer()
3726   MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun);  in LL_ADC_REG_SetOverrun()
3740   return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD));  in LL_ADC_REG_GetOverrun()
3998     preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL);  in LL_ADC_SetAnalogWDMonitChannels()
4091   __IO const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1,  in LL_ADC_GetAnalogWDMonitChannels()