Lines Matching refs:APBENR1
1012 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
1014 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN); \
1021 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
1023 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN); \
1030 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
1032 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN); \
1039 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
1041 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN); \
1047 SET_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
1049 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN); \
1056 SET_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
1058 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN); \
1065 SET_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
1067 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN); \
1073 SET_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
1075 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN); \
1081 SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
1083 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN); \
1089 SET_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
1091 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN); \
1098 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
1100 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN); \
1106 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
1108 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN); \
1114 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
1116 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN); \
1123 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
1125 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN); \
1133 SET_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
1135 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN); \
1143 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
1145 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN); \
1153 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
1155 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN); \
1162 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
1164 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN); \
1170 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
1172 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN); \
1179 SET_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
1181 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN); \
1189 SET_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
1191 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN); \
1199 SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
1201 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN); \
1209 SET_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
1211 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN); \
1219 SET_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
1221 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN); \
1229 SET_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
1231 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN); \
1238 SET_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
1240 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN); \
1246 SET_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
1248 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN); \
1255 SET_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
1257 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN); \
1265 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
1267 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN); \
1275 SET_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
1277 … tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN); \
1369 #define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN)
1371 #define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN)
1373 #define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN)
1376 #define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN)
1379 #define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN)
1382 #define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN);
1384 #define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN)
1385 #define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN)
1387 #define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN)
1389 #define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN)
1391 #define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN)
1394 #define __HAL_RCC_USART4_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN)
1397 #define __HAL_RCC_USART5_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN)
1400 #define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN)
1403 #define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)
1406 #define __HAL_RCC_LPUART2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)
1408 #define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN)
1409 #define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN)
1411 #define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN)
1414 #define __HAL_RCC_CEC_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_CECEN)
1417 #define __HAL_RCC_UCPD1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN)
1420 #define __HAL_RCC_UCPD2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN)
1423 #define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_USBEN)
1426 #define __HAL_RCC_FDCAN_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN)
1428 #define __HAL_RCC_DBGMCU_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN)
1429 #define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_PWREN)
1431 #define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN)
1434 #define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN)
1437 #define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN)
1531 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) != 0U)
1533 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) != 0U)
1535 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) != 0U)
1537 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) != 0U)
1538 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) != 0U)
1540 #define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) != 0U)
1542 #define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) != 0U)
1543 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) != 0U)
1545 #define __HAL_RCC_FDCAN_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) != 0U)
1548 #define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) != 0U)
1550 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) != 0U)
1552 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) != 0U)
1554 #define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) != 0U)
1555 #define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) != 0U)
1556 #define __HAL_RCC_USART4_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) != 0U)
1558 #define __HAL_RCC_USART5_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) != 0U)
1561 #define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) != 0U)
1564 #define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)!= 0U)
1567 #define __HAL_RCC_LPUART2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)!= 0U)
1569 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) != 0U)
1570 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) != 0U)
1572 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) != 0U)
1575 #define __HAL_RCC_CEC_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) != 0U)
1578 #define __HAL_RCC_UCPD1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) != 0U)
1581 #define __HAL_RCC_UCPD2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) != 0U)
1583 #define __HAL_RCC_DBGMCU_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) != 0U)
1584 #define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) != 0U)
1586 #define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) != 0U)
1589 #define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) != 0U)
1592 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) != 0U)
1595 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM2EN) == 0U)
1597 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM3EN) == 0U)
1599 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM4EN) == 0U)
1601 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM6EN) == 0U)
1602 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_TIM7EN) == 0U)
1604 #define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CRSEN) == 0U)
1606 #define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_RTCAPBEN) == 0U)
1607 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_WWDGEN) == 0U)
1609 #define __HAL_RCC_FDCAN_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_FDCANEN) == 0U)
1612 #define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USBEN) == 0U)
1614 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI2EN) == 0U)
1616 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_SPI3EN) == 0U)
1618 #define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN) == 0U)
1619 #define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART3EN) == 0U)
1620 #define __HAL_RCC_USART4_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART4EN) == 0U)
1622 #define __HAL_RCC_USART5_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART5EN) == 0U)
1625 #define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_USART6EN) == 0U)
1628 #define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART1EN)== 0U)
1631 #define __HAL_RCC_LPUART2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPUART2EN)== 0U)
1633 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C1EN) == 0U)
1634 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C2EN) == 0U)
1636 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_I2C3EN) == 0U)
1639 #define __HAL_RCC_CEC_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_CECEN) == 0U)
1642 #define __HAL_RCC_UCPD1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD1EN) == 0U)
1645 #define __HAL_RCC_UCPD2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_UCPD2EN) == 0U)
1647 #define __HAL_RCC_DBGMCU_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DBGEN) == 0U)
1648 #define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_PWREN) == 0U)
1650 #define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_DAC1EN) == 0U)
1653 #define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM2EN) == 0U)
1656 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APBENR1, RCC_APBENR1_LPTIM1EN) == 0U)