186 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
187 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
188 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
189 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
190 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
191 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
192 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
193 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
194 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
195 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
216 ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx)  in LL_TIM_DeInit()  argument
221   assert_param(IS_TIM_INSTANCE(TIMx));  in LL_TIM_DeInit()
223   if (TIMx == TIM1)  in LL_TIM_DeInit()
228   else if (TIMx == TIM2)  in LL_TIM_DeInit()
234   else if (TIMx == TIM3)  in LL_TIM_DeInit()
241   else if (TIMx == TIM4)  in LL_TIM_DeInit()
248   else if (TIMx == TIM5)  in LL_TIM_DeInit()
255   else if (TIMx == TIM6)  in LL_TIM_DeInit()
262   else if (TIMx == TIM7)  in LL_TIM_DeInit()
269   else if (TIMx == TIM8)  in LL_TIM_DeInit()
276   else if (TIMx == TIM9)  in LL_TIM_DeInit()
283   else if (TIMx == TIM10)  in LL_TIM_DeInit()
290   else if (TIMx == TIM11)  in LL_TIM_DeInit()
297   else if (TIMx == TIM12)  in LL_TIM_DeInit()
304   else if (TIMx == TIM13)  in LL_TIM_DeInit()
311   else if (TIMx == TIM14)  in LL_TIM_DeInit()
350 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct)  in LL_TIM_Init()  argument
355   assert_param(IS_TIM_INSTANCE(TIMx));  in LL_TIM_Init()
359   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);  in LL_TIM_Init()
361   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))  in LL_TIM_Init()
367   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))  in LL_TIM_Init()
374   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);  in LL_TIM_Init()
377   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);  in LL_TIM_Init()
380   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);  in LL_TIM_Init()
382   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))  in LL_TIM_Init()
385     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);  in LL_TIM_Init()
390   LL_TIM_GenerateEvent_UPDATE(TIMx);  in LL_TIM_Init()
431 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_OC_InitTypeDef *TIM_OC…  in LL_TIM_OC_Init()  argument
438       result = OC1Config(TIMx, TIM_OC_InitStruct);  in LL_TIM_OC_Init()
441       result = OC2Config(TIMx, TIM_OC_InitStruct);  in LL_TIM_OC_Init()
444       result = OC3Config(TIMx, TIM_OC_InitStruct);  in LL_TIM_OC_Init()
447       result = OC4Config(TIMx, TIM_OC_InitStruct);  in LL_TIM_OC_Init()
450       result = OC5Config(TIMx, TIM_OC_InitStruct);  in LL_TIM_OC_Init()
453       result = OC6Config(TIMx, TIM_OC_InitStruct);  in LL_TIM_OC_Init()
492 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, const LL_TIM_IC_InitTypeDef *TIM_IC…  in LL_TIM_IC_Init()  argument
499       result = IC1Config(TIMx, TIM_IC_InitStruct);  in LL_TIM_IC_Init()
502       result = IC2Config(TIMx, TIM_IC_InitStruct);  in LL_TIM_IC_Init()
505       result = IC3Config(TIMx, TIM_IC_InitStruct);  in LL_TIM_IC_Init()
508       result = IC4Config(TIMx, TIM_IC_InitStruct);  in LL_TIM_IC_Init()
546 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, const LL_TIM_ENCODER_InitTypeDef *TIM_EncoderIni…  in LL_TIM_ENCODER_Init()  argument
552   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));  in LL_TIM_ENCODER_Init()
564   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
567   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);  in LL_TIM_ENCODER_Init()
570   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
591   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);  in LL_TIM_ENCODER_Init()
594   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);  in LL_TIM_ENCODER_Init()
597   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
639 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, const LL_TIM_HALLSENSOR_InitTypeDef *TIM_Hall…  in LL_TIM_HALLSENSOR_Init()  argument
647   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));  in LL_TIM_HALLSENSOR_Init()
653   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
656   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in LL_TIM_HALLSENSOR_Init()
659   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);  in LL_TIM_HALLSENSOR_Init()
662   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
665   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);  in LL_TIM_HALLSENSOR_Init()
694   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in LL_TIM_HALLSENSOR_Init()
697   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);  in LL_TIM_HALLSENSOR_Init()
700   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);  in LL_TIM_HALLSENSOR_Init()
703   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
706   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);  in LL_TIM_HALLSENSOR_Init()
751 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, const LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)  in LL_TIM_BDTR_Init()  argument
756   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));  in LL_TIM_BDTR_Init()
778   if (IS_TIM_BKIN2_INSTANCE(TIMx))  in LL_TIM_BDTR_Init()
791   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);  in LL_TIM_BDTR_Init()
815 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)  in OC1Config()  argument
822   assert_param(IS_TIM_CC1_INSTANCE(TIMx));  in OC1Config()
828   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
831   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
834   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC1Config()
837   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);  in OC1Config()
851   if (IS_TIM_BREAK_INSTANCE(TIMx))  in OC1Config()
872   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC1Config()
875   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);  in OC1Config()
878   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);  in OC1Config()
881   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
894 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)  in OC2Config()  argument
901   assert_param(IS_TIM_CC2_INSTANCE(TIMx));  in OC2Config()
907   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
910   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
913   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC2Config()
916   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);  in OC2Config()
930   if (IS_TIM_BREAK_INSTANCE(TIMx))  in OC2Config()
951   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC2Config()
954   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);  in OC2Config()
957   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);  in OC2Config()
960   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
973 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)  in OC3Config()  argument
980   assert_param(IS_TIM_CC3_INSTANCE(TIMx));  in OC3Config()
986   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
989   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
992   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);  in OC3Config()
995   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);  in OC3Config()
1009   if (IS_TIM_BREAK_INSTANCE(TIMx))  in OC3Config()
1030   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC3Config()
1033   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);  in OC3Config()
1036   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);  in OC3Config()
1039   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1052 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)  in OC4Config()  argument
1059   assert_param(IS_TIM_CC4_INSTANCE(TIMx));  in OC4Config()
1065   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1068   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1071   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);  in OC4Config()
1074   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);  in OC4Config()
1088   if (IS_TIM_BREAK_INSTANCE(TIMx))  in OC4Config()
1097   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);  in OC4Config()
1100   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);  in OC4Config()
1103   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);  in OC4Config()
1106   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1119 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)  in OC5Config()  argument
1125   assert_param(IS_TIM_CC5_INSTANCE(TIMx));  in OC5Config()
1133   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1136   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1139   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);  in OC5Config()
1150   if (IS_TIM_BREAK_INSTANCE(TIMx))  in OC5Config()
1156     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);  in OC5Config()
1161   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);  in OC5Config()
1164   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);  in OC5Config()
1167   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1180 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, const LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)  in OC6Config()  argument
1186   assert_param(IS_TIM_CC6_INSTANCE(TIMx));  in OC6Config()
1194   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1197   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1200   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);  in OC6Config()
1211   if (IS_TIM_BREAK_INSTANCE(TIMx))  in OC6Config()
1217     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);  in OC6Config()
1221   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);  in OC6Config()
1224   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);  in OC6Config()
1227   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1240 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)  in IC1Config()  argument
1243   assert_param(IS_TIM_CC1_INSTANCE(TIMx));  in IC1Config()
1250   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1253   MODIFY_REG(TIMx->CCMR1,  in IC1Config()
1258   MODIFY_REG(TIMx->CCER,  in IC1Config()
1273 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)  in IC2Config()  argument
1276   assert_param(IS_TIM_CC2_INSTANCE(TIMx));  in IC2Config()
1283   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1286   MODIFY_REG(TIMx->CCMR1,  in IC2Config()
1291   MODIFY_REG(TIMx->CCER,  in IC2Config()
1306 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)  in IC3Config()  argument
1309   assert_param(IS_TIM_CC3_INSTANCE(TIMx));  in IC3Config()
1316   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1319   MODIFY_REG(TIMx->CCMR2,  in IC3Config()
1324   MODIFY_REG(TIMx->CCER,  in IC3Config()
1339 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, const LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)  in IC4Config()  argument
1342   assert_param(IS_TIM_CC4_INSTANCE(TIMx));  in IC4Config()
1349   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1352   MODIFY_REG(TIMx->CCMR2,  in IC4Config()
1357   MODIFY_REG(TIMx->CCER,  in IC4Config()