564   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_ENCODER_Init()
570   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_ENCODER_Init()
597   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_ENCODER_Init()
653   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);  in LL_TIM_HALLSENSOR_Init()
662   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in LL_TIM_HALLSENSOR_Init()
703   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in LL_TIM_HALLSENSOR_Init()
828   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);  in OC1Config()
831   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC1Config()
881   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC1Config()
907   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);  in OC2Config()
910   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC2Config()
960   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC2Config()
986   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);  in OC3Config()
989   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);  in OC3Config()
1039   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC3Config()
1065   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);  in OC4Config()
1068   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC4Config()
1106   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC4Config()
1133   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);  in OC5Config()
1136   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC5Config()
1167   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC5Config()
1194   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);  in OC6Config()
1197   tmpccer = LL_TIM_ReadReg(TIMx, CCER);  in OC6Config()
1227   LL_TIM_WriteReg(TIMx, CCER, tmpccer);  in OC6Config()
1250   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;  in IC1Config()
1258   MODIFY_REG(TIMx->CCER,  in IC1Config()
1283   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;  in IC2Config()
1291   MODIFY_REG(TIMx->CCER,  in IC2Config()
1316   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;  in IC3Config()
1324   MODIFY_REG(TIMx->CCER,  in IC3Config()
1349   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;  in IC4Config()
1357   MODIFY_REG(TIMx->CCER,  in IC4Config()