Lines Matching refs:Timing
325 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_NORSRAM_Timing_Init() argument
331 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Timing_Init()
332 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Timing_Init()
333 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Timing_Init()
334 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Timing_Init()
335 assert_param(IS_FMC_CLK_DIV(Timing->CLKDivision)); in FMC_NORSRAM_Timing_Init()
336 assert_param(IS_FMC_DATA_LATENCY(Timing->DataLatency)); in FMC_NORSRAM_Timing_Init()
337 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Timing_Init()
341 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Timing_Init()
342 … ((Timing->AddressHoldTime) << FMC_BTR1_ADDHLD_Pos) | in FMC_NORSRAM_Timing_Init()
343 … ((Timing->DataSetupTime) << FMC_BTR1_DATAST_Pos) | in FMC_NORSRAM_Timing_Init()
344 … ((Timing->BusTurnAroundDuration) << FMC_BTR1_BUSTURN_Pos) | in FMC_NORSRAM_Timing_Init()
345 … (((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos) | in FMC_NORSRAM_Timing_Init()
346 … (((Timing->DataLatency) - 2U) << FMC_BTR1_DATLAT_Pos) | in FMC_NORSRAM_Timing_Init()
347 (Timing->AccessMode))); in FMC_NORSRAM_Timing_Init()
353 tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTR1_CLKDIV_Pos); in FMC_NORSRAM_Timing_Init()
373 FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, in FMC_NORSRAM_Extended_Timing_Init() argument
384 assert_param(IS_FMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
385 assert_param(IS_FMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime)); in FMC_NORSRAM_Extended_Timing_Init()
386 assert_param(IS_FMC_DATASETUP_TIME(Timing->DataSetupTime)); in FMC_NORSRAM_Extended_Timing_Init()
387 assert_param(IS_FMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration)); in FMC_NORSRAM_Extended_Timing_Init()
388 assert_param(IS_FMC_ACCESS_MODE(Timing->AccessMode)); in FMC_NORSRAM_Extended_Timing_Init()
392 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime … in FMC_NORSRAM_Extended_Timing_Init()
393 … ((Timing->AddressHoldTime) << FMC_BWTR1_ADDHLD_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
394 … ((Timing->DataSetupTime) << FMC_BWTR1_DATAST_Pos) | in FMC_NORSRAM_Extended_Timing_Init()
395 … Timing->AccessMode | in FMC_NORSRAM_Extended_Timing_Init()
396 … ((Timing->BusTurnAroundDuration) << FMC_BWTR1_BUSTURN_Pos))); in FMC_NORSRAM_Extended_Timing_Init()
551 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_CommonSpace_Timing_Init() argument
555 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
556 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
557 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
558 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_CommonSpace_Timing_Init()
565 MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_CommonSpace_Timing_Init()
566 ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT3_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
567 ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD3_Pos) | in FMC_NAND_CommonSpace_Timing_Init()
568 ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ3_Pos))); in FMC_NAND_CommonSpace_Timing_Init()
582 … FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) in FMC_NAND_AttributeSpace_Timing_Init() argument
586 assert_param(IS_FMC_SETUP_TIME(Timing->SetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
587 assert_param(IS_FMC_WAIT_TIME(Timing->WaitSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
588 assert_param(IS_FMC_HOLD_TIME(Timing->HoldSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
589 assert_param(IS_FMC_HIZ_TIME(Timing->HiZSetupTime)); in FMC_NAND_AttributeSpace_Timing_Init()
596 MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime | in FMC_NAND_AttributeSpace_Timing_Init()
597 ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT3_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
598 ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD3_Pos) | in FMC_NAND_AttributeSpace_Timing_Init()
599 ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ3_Pos))); in FMC_NAND_AttributeSpace_Timing_Init()
852 FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank) in FMC_SDRAM_Timing_Init() argument
856 assert_param(IS_FMC_LOADTOACTIVE_DELAY(Timing->LoadToActiveDelay)); in FMC_SDRAM_Timing_Init()
857 assert_param(IS_FMC_EXITSELFREFRESH_DELAY(Timing->ExitSelfRefreshDelay)); in FMC_SDRAM_Timing_Init()
858 assert_param(IS_FMC_SELFREFRESH_TIME(Timing->SelfRefreshTime)); in FMC_SDRAM_Timing_Init()
859 assert_param(IS_FMC_ROWCYCLE_DELAY(Timing->RowCycleDelay)); in FMC_SDRAM_Timing_Init()
860 assert_param(IS_FMC_WRITE_RECOVERY_TIME(Timing->WriteRecoveryTime)); in FMC_SDRAM_Timing_Init()
861 assert_param(IS_FMC_RP_DELAY(Timing->RPDelay)); in FMC_SDRAM_Timing_Init()
862 assert_param(IS_FMC_RCD_DELAY(Timing->RCDDelay)); in FMC_SDRAM_Timing_Init()
870 (((Timing->LoadToActiveDelay) - 1U) | in FMC_SDRAM_Timing_Init()
871 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | in FMC_SDRAM_Timing_Init()
872 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | in FMC_SDRAM_Timing_Init()
873 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | in FMC_SDRAM_Timing_Init()
874 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | in FMC_SDRAM_Timing_Init()
875 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos) | in FMC_SDRAM_Timing_Init()
876 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); in FMC_SDRAM_Timing_Init()
883 (((Timing->RowCycleDelay) - 1U) << FMC_SDTR1_TRC_Pos) | in FMC_SDRAM_Timing_Init()
884 (((Timing->RPDelay) - 1U) << FMC_SDTR1_TRP_Pos)); in FMC_SDRAM_Timing_Init()
888 (((Timing->LoadToActiveDelay) - 1U) | in FMC_SDRAM_Timing_Init()
889 (((Timing->ExitSelfRefreshDelay) - 1U) << FMC_SDTR1_TXSR_Pos) | in FMC_SDRAM_Timing_Init()
890 (((Timing->SelfRefreshTime) - 1U) << FMC_SDTR1_TRAS_Pos) | in FMC_SDRAM_Timing_Init()
891 (((Timing->WriteRecoveryTime) - 1U) << FMC_SDTR1_TWR_Pos) | in FMC_SDRAM_Timing_Init()
892 (((Timing->RCDDelay) - 1U) << FMC_SDTR1_TRCD_Pos))); in FMC_SDRAM_Timing_Init()