190 HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Init()  argument
198   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Init()
216   __FMC_NORSRAM_DISABLE(Device, Init->NSBank);  in FMC_NORSRAM_Init()
263   MODIFY_REG(Device->BTCR[Init->NSBank], mask, btcr_reg);  in FMC_NORSRAM_Init()
268     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN, Init->ContinuousClock);  in FMC_NORSRAM_Init()
274     SET_BIT(Device->BTCR[FMC_NORSRAM_BANK1], (uint32_t)(Init->WriteFifo));  in FMC_NORSRAM_Init()
287 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_DeInit()  argument
291   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_DeInit()
296   __FMC_NORSRAM_DISABLE(Device, Bank);  in FMC_NORSRAM_DeInit()
302     Device->BTCR[Bank] = 0x000030DBU;  in FMC_NORSRAM_DeInit()
307     Device->BTCR[Bank] = 0x000030D2U;  in FMC_NORSRAM_DeInit()
310   Device->BTCR[Bank + 1U] = 0x0FFFFFFFU;  in FMC_NORSRAM_DeInit()
324 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device,  in FMC_NORSRAM_Timing_Init()  argument
330   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_Timing_Init()
341 …MODIFY_REG(Device->BTCR[Bank + 1U], BTR_CLEAR_MASK, (Timing->AddressSetupTime                     …  in FMC_NORSRAM_Timing_Init()
350   if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN))  in FMC_NORSRAM_Timing_Init()
352     tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTR1_CLKDIV_Pos));  in FMC_NORSRAM_Timing_Init()
354     MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTR1_CLKDIV, tmpr);  in FMC_NORSRAM_Timing_Init()
372 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device,  in FMC_NORSRAM_Extended_Timing_Init()  argument
383     assert_param(IS_FMC_NORSRAM_EXTENDED_DEVICE(Device));  in FMC_NORSRAM_Extended_Timing_Init()
392 …MODIFY_REG(Device->BWTR[Bank], BWTR_CLEAR_MASK, (Timing->AddressSetupTime                         …  in FMC_NORSRAM_Extended_Timing_Init()
400     Device->BWTR[Bank] = 0x0FFFFFFFU;  in FMC_NORSRAM_Extended_Timing_Init()
430 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Enable()  argument
433   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Enable()
437   SET_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Enable()
448 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)  in FMC_NORSRAM_WriteOperation_Disable()  argument
451   assert_param(IS_FMC_NORSRAM_DEVICE(Device));  in FMC_NORSRAM_WriteOperation_Disable()
455   CLEAR_BIT(Device->BTCR[Bank], FMC_WRITE_OPERATION_ENABLE);  in FMC_NORSRAM_WriteOperation_Disable()
518 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)  in FMC_NAND_Init()  argument
521   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_Init()
531   MODIFY_REG(Device->PCR, PCR_CLEAR_MASK, (Init->Waitfeature                            |  in FMC_NAND_Init()
550 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_CommonSpace_Timing_Init()  argument
554   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_CommonSpace_Timing_Init()
565   MODIFY_REG(Device->PMEM, PMEM_CLEAR_MASK, (Timing->SetupTime                                 |  in FMC_NAND_CommonSpace_Timing_Init()
581 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device,  in FMC_NAND_AttributeSpace_Timing_Init()  argument
585   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_AttributeSpace_Timing_Init()
596   MODIFY_REG(Device->PATT, PATT_CLEAR_MASK, (Timing->SetupTime                                 |  in FMC_NAND_AttributeSpace_Timing_Init()
610 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_DeInit()  argument
613   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_DeInit()
617   __FMC_NAND_DISABLE(Device, Bank);  in FMC_NAND_DeInit()
624   WRITE_REG(Device->PCR,  0x00000018U);  in FMC_NAND_DeInit()
625   WRITE_REG(Device->SR,   0x00000040U);  in FMC_NAND_DeInit()
626   WRITE_REG(Device->PMEM, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
627   WRITE_REG(Device->PATT, 0xFCFCFCFCU);  in FMC_NAND_DeInit()
658 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Enable()  argument
661   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Enable()
668   SET_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Enable()
680 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)  in FMC_NAND_ECC_Disable()  argument
683   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_ECC_Disable()
690   CLEAR_BIT(Device->PCR, FMC_PCR_ECCEN);  in FMC_NAND_ECC_Disable()
703 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank,  in FMC_NAND_GetECC()  argument
709   assert_param(IS_FMC_NAND_DEVICE(Device));  in FMC_NAND_GetECC()
716   while (__FMC_NAND_GET_FLAG(Device, Bank, FMC_FLAG_FEMPT) == RESET)  in FMC_NAND_GetECC()
732   *ECCval = (uint32_t)Device->ECCR;  in FMC_NAND_GetECC()
789 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)  in FMC_SDRAM_Init()  argument
792   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_Init()
807     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],  in FMC_SDRAM_Init()
821     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK1],  in FMC_SDRAM_Init()
829     MODIFY_REG(Device->SDCR[FMC_SDRAM_BANK2],  in FMC_SDRAM_Init()
851 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device,  in FMC_SDRAM_Timing_Init()  argument
855   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_Timing_Init()
868     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],  in FMC_SDRAM_Timing_Init()
880     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK1],  in FMC_SDRAM_Timing_Init()
886     MODIFY_REG(Device->SDTR[FMC_SDRAM_BANK2],  in FMC_SDRAM_Timing_Init()
903 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_DeInit()  argument
906   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_DeInit()
910   Device->SDCR[Bank] = 0x000002D0U;  in FMC_SDRAM_DeInit()
911   Device->SDTR[Bank] = 0x0FFFFFFFU;  in FMC_SDRAM_DeInit()
912   Device->SDCMR      = 0x00000000U;  in FMC_SDRAM_DeInit()
913   Device->SDRTR      = 0x00000000U;  in FMC_SDRAM_DeInit()
914   Device->SDSR       = 0x00000000U;  in FMC_SDRAM_DeInit()
944 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Enable()  argument
947   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_WriteProtection_Enable()
951   SET_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Enable()
961 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_WriteProtection_Disable()  argument
964   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_WriteProtection_Disable()
968   CLEAR_BIT(Device->SDCR[Bank], FMC_SDRAM_WRITE_PROTECTION_ENABLE);  in FMC_SDRAM_WriteProtection_Disable()
981 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,  in FMC_SDRAM_SendCommand()  argument
985   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_SendCommand()
992 …MODIFY_REG(Device->SDCMR, (FMC_SDCMR_MODE | FMC_SDCMR_CTB2 | FMC_SDCMR_CTB1 | FMC_SDCMR_NRFS | FMC…  in FMC_SDRAM_SendCommand()
1007 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)  in FMC_SDRAM_ProgramRefreshRate()  argument
1010   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_ProgramRefreshRate()
1014   MODIFY_REG(Device->SDRTR, FMC_SDRTR_COUNT, (RefreshRate << FMC_SDRTR_COUNT_Pos));  in FMC_SDRAM_ProgramRefreshRate()
1025 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,  in FMC_SDRAM_SetAutoRefreshNumber()  argument
1029   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_SetAutoRefreshNumber()
1033   MODIFY_REG(Device->SDCMR, FMC_SDCMR_NRFS, ((AutoRefreshNumber - 1U) << FMC_SDCMR_NRFS_Pos));  in FMC_SDRAM_SetAutoRefreshNumber()
1047 uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)  in FMC_SDRAM_GetModeStatus()  argument
1052   assert_param(IS_FMC_SDRAM_DEVICE(Device));  in FMC_SDRAM_GetModeStatus()
1058     tmpreg = (uint32_t)(Device->SDSR & FMC_SDSR_MODES1);  in FMC_SDRAM_GetModeStatus()
1062     tmpreg = ((uint32_t)(Device->SDSR & FMC_SDSR_MODES2) >> 2U);  in FMC_SDRAM_GetModeStatus()