Lines Matching refs:hqspi
260 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, F…
261 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_…
262 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod…
292 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Init() argument
298 if(hqspi == NULL) in HAL_QSPI_Init()
304 assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance)); in HAL_QSPI_Init()
305 assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler)); in HAL_QSPI_Init()
306 assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold)); in HAL_QSPI_Init()
307 assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting)); in HAL_QSPI_Init()
308 assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize)); in HAL_QSPI_Init()
309 assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime)); in HAL_QSPI_Init()
310 assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode)); in HAL_QSPI_Init()
311 assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash)); in HAL_QSPI_Init()
313 if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE ) in HAL_QSPI_Init()
315 assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID)); in HAL_QSPI_Init()
318 if(hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_Init()
321 hqspi->Lock = HAL_UNLOCKED; in HAL_QSPI_Init()
325 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_Init()
326 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_Init()
327 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_Init()
328 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_Init()
329 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_Init()
330 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_Init()
331 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_Init()
332 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_Init()
333 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_Init()
334 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_Init()
336 if(hqspi->MspInitCallback == NULL) in HAL_QSPI_Init()
338 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_Init()
342 hqspi->MspInitCallback(hqspi); in HAL_QSPI_Init()
345 HAL_QSPI_MspInit(hqspi); in HAL_QSPI_Init()
349 HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); in HAL_QSPI_Init()
353 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_Init()
354 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_Init()
357 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Init()
362 …MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUAD… in HAL_QSPI_Init()
363 ((hqspi->Init.ClockPrescaler << QUADSPI_CR_PRESCALER_Pos) | in HAL_QSPI_Init()
364 hqspi->Init.SampleShifting | hqspi->Init.FlashID | hqspi->Init.DualFlash)); in HAL_QSPI_Init()
367 MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE), in HAL_QSPI_Init()
368 ((hqspi->Init.FlashSize << QUADSPI_DCR_FSIZE_Pos) | in HAL_QSPI_Init()
369 hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode)); in HAL_QSPI_Init()
372 __HAL_QSPI_ENABLE(hqspi); in HAL_QSPI_Init()
375 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Init()
378 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Init()
382 __HAL_UNLOCK(hqspi); in HAL_QSPI_Init()
393 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_DeInit() argument
396 if(hqspi == NULL) in HAL_QSPI_DeInit()
402 __HAL_QSPI_DISABLE(hqspi); in HAL_QSPI_DeInit()
405 if(hqspi->MspDeInitCallback == NULL) in HAL_QSPI_DeInit()
407 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_DeInit()
411 hqspi->MspDeInitCallback(hqspi); in HAL_QSPI_DeInit()
414 HAL_QSPI_MspDeInit(hqspi); in HAL_QSPI_DeInit()
418 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_DeInit()
421 hqspi->State = HAL_QSPI_STATE_RESET; in HAL_QSPI_DeInit()
424 __HAL_UNLOCK(hqspi); in HAL_QSPI_DeInit()
434 __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspInit() argument
437 UNUSED(hqspi); in HAL_QSPI_MspInit()
449 __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_MspDeInit() argument
452 UNUSED(hqspi); in HAL_QSPI_MspDeInit()
488 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_IRQHandler() argument
491 uint32_t flag = READ_REG(hqspi->Instance->SR); in HAL_QSPI_IRQHandler()
492 uint32_t itsource = READ_REG(hqspi->Instance->CR); in HAL_QSPI_IRQHandler()
497 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
499 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
502 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
504 if (hqspi->TxXferCount > 0U) in HAL_QSPI_IRQHandler()
507 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_IRQHandler()
508 hqspi->pTxBuffPtr++; in HAL_QSPI_IRQHandler()
509 hqspi->TxXferCount--; in HAL_QSPI_IRQHandler()
515 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
520 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
523 while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != RESET) in HAL_QSPI_IRQHandler()
525 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
528 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
529 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
530 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
536 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT); in HAL_QSPI_IRQHandler()
548 hqspi->FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
550 HAL_QSPI_FifoThresholdCallback(hqspi); in HAL_QSPI_IRQHandler()
558 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC); in HAL_QSPI_IRQHandler()
561 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
564 if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX) in HAL_QSPI_IRQHandler()
566 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
569 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
572 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
577 HAL_QSPI_Abort_IT(hqspi); in HAL_QSPI_IRQHandler()
581 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
585 hqspi->TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
587 HAL_QSPI_TxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
590 else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX) in HAL_QSPI_IRQHandler()
592 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
595 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
598 __HAL_DMA_DISABLE(hqspi->hdma); in HAL_QSPI_IRQHandler()
602 data_reg = &hqspi->Instance->DR; in HAL_QSPI_IRQHandler()
603 while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0U) in HAL_QSPI_IRQHandler()
605 if (hqspi->RxXferCount > 0U) in HAL_QSPI_IRQHandler()
608 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_IRQHandler()
609 hqspi->pRxBuffPtr++; in HAL_QSPI_IRQHandler()
610 hqspi->RxXferCount--; in HAL_QSPI_IRQHandler()
622 HAL_QSPI_Abort_IT(hqspi); in HAL_QSPI_IRQHandler()
626 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
630 hqspi->RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
632 HAL_QSPI_RxCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
635 else if(hqspi->State == HAL_QSPI_STATE_BUSY) in HAL_QSPI_IRQHandler()
638 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
642 hqspi->CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
644 HAL_QSPI_CmdCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
647 else if(hqspi->State == HAL_QSPI_STATE_ABORT) in HAL_QSPI_IRQHandler()
650 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_IRQHandler()
653 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
655 if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE) in HAL_QSPI_IRQHandler()
661 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
663 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_IRQHandler()
672 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
674 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
688 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM); in HAL_QSPI_IRQHandler()
691 if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0U) in HAL_QSPI_IRQHandler()
694 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_IRQHandler()
697 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
702 hqspi->StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
704 HAL_QSPI_StatusMatchCallback(hqspi); in HAL_QSPI_IRQHandler()
712 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE); in HAL_QSPI_IRQHandler()
715 __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT); in HAL_QSPI_IRQHandler()
718 hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER; in HAL_QSPI_IRQHandler()
720 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_IRQHandler()
723 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_IRQHandler()
726 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_IRQHandler()
727 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_IRQHandler()
730 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_IRQHandler()
733 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
737 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
739 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
746 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_IRQHandler()
750 hqspi->ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
752 HAL_QSPI_ErrorCallback(hqspi); in HAL_QSPI_IRQHandler()
761 WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO); in HAL_QSPI_IRQHandler()
765 hqspi->TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
767 HAL_QSPI_TimeOutCallback(hqspi); in HAL_QSPI_IRQHandler()
785 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Ti… in HAL_QSPI_Command() argument
817 __HAL_LOCK(hqspi); in HAL_QSPI_Command()
819 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command()
821 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command()
824 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command()
827 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_Command()
832 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command()
838 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Command()
842 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Command()
845 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
851 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command()
861 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command()
874 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd) in HAL_QSPI_Command_IT() argument
905 __HAL_LOCK(hqspi); in HAL_QSPI_Command_IT()
907 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Command_IT()
909 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Command_IT()
912 hqspi->State = HAL_QSPI_STATE_BUSY; in HAL_QSPI_Command_IT()
915 status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); in HAL_QSPI_Command_IT()
922 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Command_IT()
926 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Command_IT()
933 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
936 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC); in HAL_QSPI_Command_IT()
941 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Command_IT()
944 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
950 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
958 __HAL_UNLOCK(hqspi); in HAL_QSPI_Command_IT()
973 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Transmit() argument
977 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Transmit()
980 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit()
982 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit()
984 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit()
989 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit()
992 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
993 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit()
994 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit()
997 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit()
999 while(hqspi->TxXferCount > 0U) in HAL_QSPI_Transmit()
1002 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1009 *((__IO uint8_t *)data_reg) = *hqspi->pTxBuffPtr; in HAL_QSPI_Transmit()
1010 hqspi->pTxBuffPtr++; in HAL_QSPI_Transmit()
1011 hqspi->TxXferCount--; in HAL_QSPI_Transmit()
1017 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Transmit()
1022 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Transmit()
1026 status = HAL_QSPI_Abort(hqspi); in HAL_QSPI_Transmit()
1032 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit()
1036 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit()
1046 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit()
1060 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout) in HAL_QSPI_Receive() argument
1064 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive()
1065 __IO uint32_t *data_reg = &hqspi->Instance->DR; in HAL_QSPI_Receive()
1068 __HAL_LOCK(hqspi); in HAL_QSPI_Receive()
1070 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive()
1072 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive()
1077 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive()
1080 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1081 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive()
1082 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive()
1085 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive()
1088 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive()
1090 while(hqspi->RxXferCount > 0U) in HAL_QSPI_Receive()
1093 …status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Time… in HAL_QSPI_Receive()
1100 *hqspi->pRxBuffPtr = *((__IO uint8_t *)data_reg); in HAL_QSPI_Receive()
1101 hqspi->pRxBuffPtr++; in HAL_QSPI_Receive()
1102 hqspi->RxXferCount--; in HAL_QSPI_Receive()
1108 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout); in HAL_QSPI_Receive()
1113 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Receive()
1117 status = HAL_QSPI_Abort(hqspi); in HAL_QSPI_Receive()
1123 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive()
1127 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive()
1137 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive()
1149 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_IT() argument
1154 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_IT()
1156 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_IT()
1158 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_IT()
1163 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_IT()
1166 hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1167 hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Transmit_IT()
1168 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_IT()
1171 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Transmit_IT()
1174 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_IT()
1177 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1180 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Transmit_IT()
1184 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_IT()
1188 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1196 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_IT()
1209 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_IT() argument
1212 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_IT()
1215 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_IT()
1217 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_IT()
1219 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_IT()
1224 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_IT()
1227 hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1228 hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1U; in HAL_QSPI_Receive_IT()
1229 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_IT()
1232 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC); in HAL_QSPI_Receive_IT()
1235 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_IT()
1238 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_IT()
1241 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1244 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC); in HAL_QSPI_Receive_IT()
1248 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_IT()
1252 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1260 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_IT()
1277 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Transmit_DMA() argument
1280 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Transmit_DMA()
1283 __HAL_LOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1285 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Transmit_DMA()
1288 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Transmit_DMA()
1293 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Transmit_DMA()
1295 hqspi->TxXferCount = data_size; in HAL_QSPI_Transmit_DMA()
1297 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Transmit_DMA()
1299 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Transmit_DMA()
1303 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1307 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1311 hqspi->TxXferCount = (data_size >> 1U); in HAL_QSPI_Transmit_DMA()
1314 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Transmit_DMA()
1316 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Transmit_DMA()
1320 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1324 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1328 hqspi->TxXferCount = (data_size >> 2U); in HAL_QSPI_Transmit_DMA()
1339 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX; in HAL_QSPI_Transmit_DMA()
1342 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Transmit_DMA()
1345 hqspi->TxXferSize = hqspi->TxXferCount; in HAL_QSPI_Transmit_DMA()
1346 hqspi->pTxBuffPtr = pData; in HAL_QSPI_Transmit_DMA()
1349 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); in HAL_QSPI_Transmit_DMA()
1352 hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt; in HAL_QSPI_Transmit_DMA()
1355 hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt; in HAL_QSPI_Transmit_DMA()
1358 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Transmit_DMA()
1361 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Transmit_DMA()
1364 hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH; in HAL_QSPI_Transmit_DMA()
1365 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Transmit_DMA()
1368 …if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)pData, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSi… in HAL_QSPI_Transmit_DMA()
1371 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1374 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Transmit_DMA()
1377 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Transmit_DMA()
1382 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Transmit_DMA()
1383 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Transmit_DMA()
1386 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1392 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Transmit_DMA()
1396 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1404 __HAL_UNLOCK(hqspi); in HAL_QSPI_Transmit_DMA()
1421 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData) in HAL_QSPI_Receive_DMA() argument
1424 uint32_t addr_reg = READ_REG(hqspi->Instance->AR); in HAL_QSPI_Receive_DMA()
1425 uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1U); in HAL_QSPI_Receive_DMA()
1428 __HAL_LOCK(hqspi); in HAL_QSPI_Receive_DMA()
1430 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_Receive_DMA()
1433 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_Receive_DMA()
1438 if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE) in HAL_QSPI_Receive_DMA()
1440 hqspi->RxXferCount = data_size; in HAL_QSPI_Receive_DMA()
1442 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD) in HAL_QSPI_Receive_DMA()
1444 if (((data_size % 2U) != 0U) || ((hqspi->Init.FifoThreshold % 2U) != 0U)) in HAL_QSPI_Receive_DMA()
1448 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1452 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1456 hqspi->RxXferCount = (data_size >> 1U); in HAL_QSPI_Receive_DMA()
1459 else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD) in HAL_QSPI_Receive_DMA()
1461 if (((data_size % 4U) != 0U) || ((hqspi->Init.FifoThreshold % 4U) != 0U)) in HAL_QSPI_Receive_DMA()
1465 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1469 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1473 hqspi->RxXferCount = (data_size >> 2U); in HAL_QSPI_Receive_DMA()
1484 hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX; in HAL_QSPI_Receive_DMA()
1487 __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC)); in HAL_QSPI_Receive_DMA()
1490 hqspi->RxXferSize = hqspi->RxXferCount; in HAL_QSPI_Receive_DMA()
1491 hqspi->pRxBuffPtr = pData; in HAL_QSPI_Receive_DMA()
1494 hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt; in HAL_QSPI_Receive_DMA()
1497 hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt; in HAL_QSPI_Receive_DMA()
1500 hqspi->hdma->XferErrorCallback = QSPI_DMAError; in HAL_QSPI_Receive_DMA()
1503 hqspi->hdma->XferAbortCallback = NULL; in HAL_QSPI_Receive_DMA()
1506 hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY; in HAL_QSPI_Receive_DMA()
1507 MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction); in HAL_QSPI_Receive_DMA()
1510 …if (HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, (uint32_t)pData, hqspi->RxXferSi… in HAL_QSPI_Receive_DMA()
1513 MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ); in HAL_QSPI_Receive_DMA()
1516 WRITE_REG(hqspi->Instance->AR, addr_reg); in HAL_QSPI_Receive_DMA()
1519 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1522 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE); in HAL_QSPI_Receive_DMA()
1525 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Receive_DMA()
1530 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Receive_DMA()
1531 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Receive_DMA()
1534 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1540 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM; in HAL_QSPI_Receive_DMA()
1544 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1552 __HAL_UNLOCK(hqspi); in HAL_QSPI_Receive_DMA()
1567 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_Au… in HAL_QSPI_AutoPolling() argument
1603 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling()
1605 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling()
1607 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling()
1610 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling()
1613 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1618 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling()
1621 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling()
1624 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling()
1628 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling()
1633 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling()
1636 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout); in HAL_QSPI_AutoPolling()
1640 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM); in HAL_QSPI_AutoPolling()
1643 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_AutoPolling()
1653 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling()
1667 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI… in HAL_QSPI_AutoPolling_IT() argument
1703 __HAL_LOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1705 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_AutoPolling_IT()
1707 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_AutoPolling_IT()
1710 hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING; in HAL_QSPI_AutoPolling_IT()
1713 status = QSPI_WaitFlagStateUntilTimeout_CPUCycle(hqspi, QSPI_FLAG_BUSY, RESET, hqspi->Timeout); in HAL_QSPI_AutoPolling_IT()
1718 WRITE_REG(hqspi->Instance->PSMAR, cfg->Match); in HAL_QSPI_AutoPolling_IT()
1721 WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask); in HAL_QSPI_AutoPolling_IT()
1724 WRITE_REG(hqspi->Instance->PIR, cfg->Interval); in HAL_QSPI_AutoPolling_IT()
1727 MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS), in HAL_QSPI_AutoPolling_IT()
1731 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM); in HAL_QSPI_AutoPolling_IT()
1735 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING); in HAL_QSPI_AutoPolling_IT()
1738 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1741 __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE)); in HAL_QSPI_AutoPolling_IT()
1747 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1755 __HAL_UNLOCK(hqspi); in HAL_QSPI_AutoPolling_IT()
1770 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_M… in HAL_QSPI_MemoryMapped() argument
1804 __HAL_LOCK(hqspi); in HAL_QSPI_MemoryMapped()
1806 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_MemoryMapped()
1808 hqspi->ErrorCode = HAL_QSPI_ERROR_NONE; in HAL_QSPI_MemoryMapped()
1811 hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED; in HAL_QSPI_MemoryMapped()
1814 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_MemoryMapped()
1819 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation); in HAL_QSPI_MemoryMapped()
1826 WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod); in HAL_QSPI_MemoryMapped()
1829 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO); in HAL_QSPI_MemoryMapped()
1832 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO); in HAL_QSPI_MemoryMapped()
1836 QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED); in HAL_QSPI_MemoryMapped()
1845 __HAL_UNLOCK(hqspi); in HAL_QSPI_MemoryMapped()
1856 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_ErrorCallback() argument
1859 UNUSED(hqspi); in HAL_QSPI_ErrorCallback()
1871 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_AbortCpltCallback() argument
1874 UNUSED(hqspi); in HAL_QSPI_AbortCpltCallback()
1886 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_CmdCpltCallback() argument
1889 UNUSED(hqspi); in HAL_QSPI_CmdCpltCallback()
1901 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxCpltCallback() argument
1904 UNUSED(hqspi); in HAL_QSPI_RxCpltCallback()
1916 __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxCpltCallback() argument
1919 UNUSED(hqspi); in HAL_QSPI_TxCpltCallback()
1931 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_RxHalfCpltCallback() argument
1934 UNUSED(hqspi); in HAL_QSPI_RxHalfCpltCallback()
1946 __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TxHalfCpltCallback() argument
1949 UNUSED(hqspi); in HAL_QSPI_TxHalfCpltCallback()
1961 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_FifoThresholdCallback() argument
1964 UNUSED(hqspi); in HAL_QSPI_FifoThresholdCallback()
1976 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_StatusMatchCallback() argument
1979 UNUSED(hqspi); in HAL_QSPI_StatusMatchCallback()
1991 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_TimeOutCallback() argument
1994 UNUSED(hqspi); in HAL_QSPI_TimeOutCallback()
2022 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef … in HAL_QSPI_RegisterCallback() argument
2029 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2034 __HAL_LOCK(hqspi); in HAL_QSPI_RegisterCallback()
2036 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_RegisterCallback()
2041 hqspi->ErrorCallback = pCallback; in HAL_QSPI_RegisterCallback()
2044 hqspi->AbortCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2047 hqspi->FifoThresholdCallback = pCallback; in HAL_QSPI_RegisterCallback()
2050 hqspi->CmdCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2053 hqspi->RxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2056 hqspi->TxCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2059 hqspi->RxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2062 hqspi->TxHalfCpltCallback = pCallback; in HAL_QSPI_RegisterCallback()
2065 hqspi->StatusMatchCallback = pCallback; in HAL_QSPI_RegisterCallback()
2068 hqspi->TimeOutCallback = pCallback; in HAL_QSPI_RegisterCallback()
2071 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2074 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2078 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2084 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_RegisterCallback()
2089 hqspi->MspInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2092 hqspi->MspDeInitCallback = pCallback; in HAL_QSPI_RegisterCallback()
2096 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2105 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_RegisterCallback()
2111 __HAL_UNLOCK(hqspi); in HAL_QSPI_RegisterCallback()
2135 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDe… in HAL_QSPI_UnRegisterCallback() argument
2140 __HAL_LOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2142 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_UnRegisterCallback()
2147 hqspi->ErrorCallback = HAL_QSPI_ErrorCallback; in HAL_QSPI_UnRegisterCallback()
2150 hqspi->AbortCpltCallback = HAL_QSPI_AbortCpltCallback; in HAL_QSPI_UnRegisterCallback()
2153 hqspi->FifoThresholdCallback = HAL_QSPI_FifoThresholdCallback; in HAL_QSPI_UnRegisterCallback()
2156 hqspi->CmdCpltCallback = HAL_QSPI_CmdCpltCallback; in HAL_QSPI_UnRegisterCallback()
2159 hqspi->RxCpltCallback = HAL_QSPI_RxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2162 hqspi->TxCpltCallback = HAL_QSPI_TxCpltCallback; in HAL_QSPI_UnRegisterCallback()
2165 hqspi->RxHalfCpltCallback = HAL_QSPI_RxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2168 hqspi->TxHalfCpltCallback = HAL_QSPI_TxHalfCpltCallback; in HAL_QSPI_UnRegisterCallback()
2171 hqspi->StatusMatchCallback = HAL_QSPI_StatusMatchCallback; in HAL_QSPI_UnRegisterCallback()
2174 hqspi->TimeOutCallback = HAL_QSPI_TimeOutCallback; in HAL_QSPI_UnRegisterCallback()
2177 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2180 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2184 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2190 else if (hqspi->State == HAL_QSPI_STATE_RESET) in HAL_QSPI_UnRegisterCallback()
2195 hqspi->MspInitCallback = HAL_QSPI_MspInit; in HAL_QSPI_UnRegisterCallback()
2198 hqspi->MspDeInitCallback = HAL_QSPI_MspDeInit; in HAL_QSPI_UnRegisterCallback()
2202 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2211 hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_CALLBACK; in HAL_QSPI_UnRegisterCallback()
2217 __HAL_UNLOCK(hqspi); in HAL_QSPI_UnRegisterCallback()
2249 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetState() argument
2252 return hqspi->State; in HAL_QSPI_GetState()
2260 uint32_t HAL_QSPI_GetError(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetError() argument
2262 return hqspi->ErrorCode; in HAL_QSPI_GetError()
2270 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort() argument
2276 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort()
2279 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort()
2281 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort()
2284 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort()
2287 status = HAL_DMA_Abort(hqspi->hdma); in HAL_QSPI_Abort()
2290 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in HAL_QSPI_Abort()
2294 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort()
2297 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort()
2300 status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2304 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort()
2307 … status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout); in HAL_QSPI_Abort()
2313 CLEAR_BIT(hqspi->Instance->CCR, QUADSPI_CCR_FMODE); in HAL_QSPI_Abort()
2316 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2322 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort()
2334 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi) in HAL_QSPI_Abort_IT() argument
2339 if (((uint32_t)hqspi->State & 0x2U) != 0U) in HAL_QSPI_Abort_IT()
2342 __HAL_UNLOCK(hqspi); in HAL_QSPI_Abort_IT()
2345 hqspi->State = HAL_QSPI_STATE_ABORT; in HAL_QSPI_Abort_IT()
2348 __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE)); in HAL_QSPI_Abort_IT()
2350 if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN) != 0U) in HAL_QSPI_Abort_IT()
2353 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in HAL_QSPI_Abort_IT()
2356 hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt; in HAL_QSPI_Abort_IT()
2357 if (HAL_DMA_Abort_IT(hqspi->hdma) != HAL_OK) in HAL_QSPI_Abort_IT()
2360 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2364 hqspi->AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2366 HAL_QSPI_AbortCpltCallback(hqspi); in HAL_QSPI_Abort_IT()
2372 if (__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_BUSY) != RESET) in HAL_QSPI_Abort_IT()
2375 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in HAL_QSPI_Abort_IT()
2378 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in HAL_QSPI_Abort_IT()
2381 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in HAL_QSPI_Abort_IT()
2386 hqspi->State = HAL_QSPI_STATE_READY; in HAL_QSPI_Abort_IT()
2398 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout) in HAL_QSPI_SetTimeout() argument
2400 hqspi->Timeout = Timeout; in HAL_QSPI_SetTimeout()
2408 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold) in HAL_QSPI_SetFifoThreshold() argument
2413 __HAL_LOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2415 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFifoThreshold()
2418 hqspi->Init.FifoThreshold = Threshold; in HAL_QSPI_SetFifoThreshold()
2421 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, in HAL_QSPI_SetFifoThreshold()
2422 ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos)); in HAL_QSPI_SetFifoThreshold()
2430 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFifoThreshold()
2440 uint32_t HAL_QSPI_GetFifoThreshold(const QSPI_HandleTypeDef *hqspi) in HAL_QSPI_GetFifoThreshold() argument
2442 return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U); in HAL_QSPI_GetFifoThreshold()
2452 HAL_StatusTypeDef HAL_QSPI_SetFlashID(QSPI_HandleTypeDef *hqspi, uint32_t FlashID) in HAL_QSPI_SetFlashID() argument
2460 __HAL_LOCK(hqspi); in HAL_QSPI_SetFlashID()
2462 if(hqspi->State == HAL_QSPI_STATE_READY) in HAL_QSPI_SetFlashID()
2465 hqspi->Init.FlashID = FlashID; in HAL_QSPI_SetFlashID()
2468 MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FSEL, FlashID); in HAL_QSPI_SetFlashID()
2476 __HAL_UNLOCK(hqspi); in HAL_QSPI_SetFlashID()
2501 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxCplt() local
2502 hqspi->RxXferCount = 0U; in QSPI_DMARxCplt()
2505 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMARxCplt()
2515 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxCplt() local
2516 hqspi->TxXferCount = 0U; in QSPI_DMATxCplt()
2519 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMATxCplt()
2529 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMARxHalfCplt() local
2532 hqspi->RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2534 HAL_QSPI_RxHalfCpltCallback(hqspi); in QSPI_DMARxHalfCplt()
2545 QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)(hdma->Parent); in QSPI_DMATxHalfCplt() local
2548 hqspi->TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2550 HAL_QSPI_TxHalfCpltCallback(hqspi); in QSPI_DMATxHalfCplt()
2561 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAError() local
2566 hqspi->RxXferCount = 0U; in QSPI_DMAError()
2567 hqspi->TxXferCount = 0U; in QSPI_DMAError()
2568 hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA; in QSPI_DMAError()
2571 CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN); in QSPI_DMAError()
2574 (void)HAL_QSPI_Abort_IT(hqspi); in QSPI_DMAError()
2586 QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )(hdma->Parent); in QSPI_DMAAbortCplt() local
2588 hqspi->RxXferCount = 0U; in QSPI_DMAAbortCplt()
2589 hqspi->TxXferCount = 0U; in QSPI_DMAAbortCplt()
2591 if(hqspi->State == HAL_QSPI_STATE_ABORT) in QSPI_DMAAbortCplt()
2595 __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC); in QSPI_DMAAbortCplt()
2598 __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC); in QSPI_DMAAbortCplt()
2601 SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT); in QSPI_DMAAbortCplt()
2607 hqspi->State = HAL_QSPI_STATE_READY; in QSPI_DMAAbortCplt()
2611 hqspi->ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2613 HAL_QSPI_ErrorCallback(hqspi); in QSPI_DMAAbortCplt()
2627 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, in QSPI_WaitFlagStateUntilTimeout() argument
2631 while((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State) in QSPI_WaitFlagStateUntilTimeout()
2638 hqspi->State = HAL_QSPI_STATE_ERROR; in QSPI_WaitFlagStateUntilTimeout()
2639 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; in QSPI_WaitFlagStateUntilTimeout()
2656 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout_CPUCycle(QSPI_HandleTypeDef *hqspi, uint32_… in QSPI_WaitFlagStateUntilTimeout_CPUCycle() argument
2663 hqspi->State = HAL_QSPI_STATE_ERROR; in QSPI_WaitFlagStateUntilTimeout_CPUCycle()
2664 hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT; in QSPI_WaitFlagStateUntilTimeout_CPUCycle()
2668 while ((__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State); in QSPI_WaitFlagStateUntilTimeout_CPUCycle()
2685 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMod… in QSPI_Config() argument
2692 WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1U)); in QSPI_Config()
2700 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2706 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2715 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2722 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2735 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2743 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2750 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2762 WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes); in QSPI_Config()
2768 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2777 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2784 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2796 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()
2804 WRITE_REG(hqspi->Instance->AR, cmd->Address); in QSPI_Config()
2813 WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode | in QSPI_Config()