453   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;  in HAL_DSI_Init()
454   hdsi->Instance->WPCR[0U] |= unitIntervalx4;  in HAL_DSI_Init()
2614         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2615         hdsi->Instance->WPCR[1U] |= Value << 16U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2620         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2621         hdsi->Instance->WPCR[1U] |= Value << 18U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2635         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2636         hdsi->Instance->WPCR[1U] |= Value << 6U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2641         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2642         hdsi->Instance->WPCR[1U] |= Value << 8U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2656         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2657         hdsi->Instance->WPCR[1U] |= Value;  in HAL_DSI_SetSlewRateAndDelayTuning()
2662         hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;  in HAL_DSI_SetSlewRateAndDelayTuning()
2663         hdsi->Instance->WPCR[1U] |= Value << 2U;  in HAL_DSI_SetSlewRateAndDelayTuning()
2696   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;  in HAL_DSI_SetLowPowerRXFilter()
2697   hdsi->Instance->WPCR[1U] |= Frequency << 25U;  in HAL_DSI_SetLowPowerRXFilter()
2722   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;  in HAL_DSI_SetSDD()
2723   hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);  in HAL_DSI_SetSDD()
2759         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;  in HAL_DSI_SetLanePinsConfiguration()
2760         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U);  in HAL_DSI_SetLanePinsConfiguration()
2765         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0;  in HAL_DSI_SetLanePinsConfiguration()
2766         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U);  in HAL_DSI_SetLanePinsConfiguration()
2771         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;  in HAL_DSI_SetLanePinsConfiguration()
2772         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);  in HAL_DSI_SetLanePinsConfiguration()
2786         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;  in HAL_DSI_SetLanePinsConfiguration()
2787         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U);  in HAL_DSI_SetLanePinsConfiguration()
2792         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0;  in HAL_DSI_SetLanePinsConfiguration()
2793         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U);  in HAL_DSI_SetLanePinsConfiguration()
2798         hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;  in HAL_DSI_SetLanePinsConfiguration()
2799         hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);  in HAL_DSI_SetLanePinsConfiguration()
2842       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;  in HAL_DSI_SetPHYTimings()
2843       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);  in HAL_DSI_SetPHYTimings()
2848         hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;  in HAL_DSI_SetPHYTimings()
2849         hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;  in HAL_DSI_SetPHYTimings()
2855       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;  in HAL_DSI_SetPHYTimings()
2856       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);  in HAL_DSI_SetPHYTimings()
2861         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;  in HAL_DSI_SetPHYTimings()
2862         hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;  in HAL_DSI_SetPHYTimings()
2868       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;  in HAL_DSI_SetPHYTimings()
2869       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);  in HAL_DSI_SetPHYTimings()
2874         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;  in HAL_DSI_SetPHYTimings()
2875         hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;  in HAL_DSI_SetPHYTimings()
2881       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;  in HAL_DSI_SetPHYTimings()
2882       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);  in HAL_DSI_SetPHYTimings()
2887         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;  in HAL_DSI_SetPHYTimings()
2888         hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;  in HAL_DSI_SetPHYTimings()
2894       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;  in HAL_DSI_SetPHYTimings()
2895       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);  in HAL_DSI_SetPHYTimings()
2900         hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;  in HAL_DSI_SetPHYTimings()
2901         hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;  in HAL_DSI_SetPHYTimings()
2907       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;  in HAL_DSI_SetPHYTimings()
2908       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);  in HAL_DSI_SetPHYTimings()
2913         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;  in HAL_DSI_SetPHYTimings()
2914         hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;  in HAL_DSI_SetPHYTimings()
2920       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;  in HAL_DSI_SetPHYTimings()
2921       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);  in HAL_DSI_SetPHYTimings()
2926         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;  in HAL_DSI_SetPHYTimings()
2927         hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;  in HAL_DSI_SetPHYTimings()
2933       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;  in HAL_DSI_SetPHYTimings()
2934       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);  in HAL_DSI_SetPHYTimings()
2939         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;  in HAL_DSI_SetPHYTimings()
2940         hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;  in HAL_DSI_SetPHYTimings()
2946       hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;  in HAL_DSI_SetPHYTimings()
2947       hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);  in HAL_DSI_SetPHYTimings()
2952         hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;  in HAL_DSI_SetPHYTimings()
2953         hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;  in HAL_DSI_SetPHYTimings()
2988     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL;  in HAL_DSI_ForceTXStopMode()
2989     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U);  in HAL_DSI_ForceTXStopMode()
2994     hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;  in HAL_DSI_ForceTXStopMode()
2995     hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);  in HAL_DSI_ForceTXStopMode()
3027   hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;  in HAL_DSI_ForceRXLowPower()
3028   hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);  in HAL_DSI_ForceRXLowPower()
3052   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;  in HAL_DSI_ForceDataLanesInRX()
3053   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);  in HAL_DSI_ForceDataLanesInRX()
3077   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;  in HAL_DSI_SetPullDown()
3078   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);  in HAL_DSI_SetPullDown()
3102   hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;  in HAL_DSI_SetContentionDetectionOff()
3103   hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);  in HAL_DSI_SetContentionDetectionOff()