352         if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)  in HAL_DMA2D_DeInit()
369   hdma2d->Instance->FGPFCCR  =    0U;  in HAL_DMA2D_DeInit()
967     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_EnableCLUT()
1017     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTStartLoad()
1021     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTStartLoad()
1075     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTStartLoad_IT()
1082     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTStartLoad_IT()
1135     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTLoad()
1139     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTLoad()
1195     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_CLUTLoad_IT()
1202     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);  in HAL_DMA2D_CLUTLoad_IT()
1228     reg  = &(hdma2d->Instance->FGPFCCR);  in HAL_DMA2D_CLUTLoading_Abort()
1286     reg  = &(hdma2d->Instance->FGPFCCR);  in HAL_DMA2D_CLUTLoading_Suspend()
1359       if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)  in HAL_DMA2D_CLUTLoading_Resume()
1438   layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;  in HAL_DMA2D_PollForTransfer()
1811     MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);  in HAL_DMA2D_ConfigLayer()
1876     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),  in HAL_DMA2D_ConfigCLUT()