Lines Matching refs:hdma
133 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32…
134 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
135 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma);
171 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) in HAL_DMA_Init() argument
178 if(hdma == NULL) in HAL_DMA_Init()
184 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_Init()
185 assert_param(IS_DMA_CHANNEL(hdma->Init.Channel)); in HAL_DMA_Init()
186 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); in HAL_DMA_Init()
187 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); in HAL_DMA_Init()
188 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); in HAL_DMA_Init()
189 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); in HAL_DMA_Init()
190 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); in HAL_DMA_Init()
191 assert_param(IS_DMA_MODE(hdma->Init.Mode)); in HAL_DMA_Init()
192 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); in HAL_DMA_Init()
193 assert_param(IS_DMA_FIFO_MODE_STATE(hdma->Init.FIFOMode)); in HAL_DMA_Init()
196 if(hdma->Init.FIFOMode != DMA_FIFOMODE_DISABLE) in HAL_DMA_Init()
198 assert_param(IS_DMA_FIFO_THRESHOLD(hdma->Init.FIFOThreshold)); in HAL_DMA_Init()
199 assert_param(IS_DMA_MEMORY_BURST(hdma->Init.MemBurst)); in HAL_DMA_Init()
200 assert_param(IS_DMA_PERIPHERAL_BURST(hdma->Init.PeriphBurst)); in HAL_DMA_Init()
204 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Init()
207 __HAL_UNLOCK(hdma); in HAL_DMA_Init()
211 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Init()
214 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Init()
220 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Init()
223 hdma->State = HAL_DMA_STATE_TIMEOUT; in HAL_DMA_Init()
230 tmp = hdma->Instance->CR; in HAL_DMA_Init()
239 tmp |= hdma->Init.Channel | hdma->Init.Direction | in HAL_DMA_Init()
240 hdma->Init.PeriphInc | hdma->Init.MemInc | in HAL_DMA_Init()
241 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | in HAL_DMA_Init()
242 hdma->Init.Mode | hdma->Init.Priority; in HAL_DMA_Init()
245 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
248 tmp |= hdma->Init.MemBurst | hdma->Init.PeriphBurst; in HAL_DMA_Init()
252 hdma->Instance->CR = tmp; in HAL_DMA_Init()
255 tmp = hdma->Instance->FCR; in HAL_DMA_Init()
261 tmp |= hdma->Init.FIFOMode; in HAL_DMA_Init()
264 if(hdma->Init.FIFOMode == DMA_FIFOMODE_ENABLE) in HAL_DMA_Init()
267 tmp |= hdma->Init.FIFOThreshold; in HAL_DMA_Init()
271 if (hdma->Init.MemBurst != DMA_MBURST_SINGLE) in HAL_DMA_Init()
273 if (DMA_CheckFifoParam(hdma) != HAL_OK) in HAL_DMA_Init()
276 hdma->ErrorCode = HAL_DMA_ERROR_PARAM; in HAL_DMA_Init()
279 hdma->State = HAL_DMA_STATE_RESET; in HAL_DMA_Init()
287 hdma->Instance->FCR = tmp; in HAL_DMA_Init()
291 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_Init()
294 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_Init()
297 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Init()
300 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Init()
311 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) in HAL_DMA_DeInit() argument
316 if(hdma == NULL) in HAL_DMA_DeInit()
322 if(hdma->State == HAL_DMA_STATE_BUSY) in HAL_DMA_DeInit()
329 assert_param(IS_DMA_STREAM_ALL_INSTANCE(hdma->Instance)); in HAL_DMA_DeInit()
332 __HAL_DMA_DISABLE(hdma); in HAL_DMA_DeInit()
335 hdma->Instance->CR = 0U; in HAL_DMA_DeInit()
338 hdma->Instance->NDTR = 0U; in HAL_DMA_DeInit()
341 hdma->Instance->PAR = 0U; in HAL_DMA_DeInit()
344 hdma->Instance->M0AR = 0U; in HAL_DMA_DeInit()
347 hdma->Instance->M1AR = 0U; in HAL_DMA_DeInit()
350 hdma->Instance->FCR = (uint32_t)0x00000021U; in HAL_DMA_DeInit()
353 regs = (DMA_Base_Registers *)DMA_CalcBaseAndBitshift(hdma); in HAL_DMA_DeInit()
356 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_DeInit()
359 hdma->XferCpltCallback = NULL; in HAL_DMA_DeInit()
360 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_DeInit()
361 hdma->XferM1CpltCallback = NULL; in HAL_DMA_DeInit()
362 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_DeInit()
363 hdma->XferErrorCallback = NULL; in HAL_DMA_DeInit()
364 hdma->XferAbortCallback = NULL; in HAL_DMA_DeInit()
367 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_DeInit()
370 hdma->State = HAL_DMA_STATE_RESET; in HAL_DMA_DeInit()
373 __HAL_UNLOCK(hdma); in HAL_DMA_DeInit()
409 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, … in HAL_DMA_Start() argument
417 __HAL_LOCK(hdma); in HAL_DMA_Start()
419 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start()
422 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start()
425 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start()
428 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start()
431 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start()
436 __HAL_UNLOCK(hdma); in HAL_DMA_Start()
453 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddres… in HAL_DMA_Start_IT() argument
458 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Start_IT()
464 __HAL_LOCK(hdma); in HAL_DMA_Start_IT()
466 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_Start_IT()
469 hdma->State = HAL_DMA_STATE_BUSY; in HAL_DMA_Start_IT()
472 hdma->ErrorCode = HAL_DMA_ERROR_NONE; in HAL_DMA_Start_IT()
475 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); in HAL_DMA_Start_IT()
478 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_Start_IT()
481 hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME; in HAL_DMA_Start_IT()
482 hdma->Instance->FCR |= DMA_IT_FE; in HAL_DMA_Start_IT()
484 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_Start_IT()
486 hdma->Instance->CR |= DMA_IT_HT; in HAL_DMA_Start_IT()
490 __HAL_DMA_ENABLE(hdma); in HAL_DMA_Start_IT()
495 __HAL_UNLOCK(hdma); in HAL_DMA_Start_IT()
516 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort() argument
519 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_Abort()
523 if(hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort()
525 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort()
528 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
535 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); in HAL_DMA_Abort()
536 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_Abort()
538 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) in HAL_DMA_Abort()
540 hdma->Instance->CR &= ~(DMA_IT_HT); in HAL_DMA_Abort()
544 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort()
547 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET) in HAL_DMA_Abort()
553 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_Abort()
556 hdma->State = HAL_DMA_STATE_TIMEOUT; in HAL_DMA_Abort()
559 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
566 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_Abort()
569 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_Abort()
572 __HAL_UNLOCK(hdma); in HAL_DMA_Abort()
584 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) in HAL_DMA_Abort_IT() argument
586 if(hdma->State != HAL_DMA_STATE_BUSY) in HAL_DMA_Abort_IT()
588 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_Abort_IT()
594 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_Abort_IT()
597 __HAL_DMA_DISABLE(hdma); in HAL_DMA_Abort_IT()
614 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef Com… in HAL_DMA_PollForTransfer() argument
624 if(HAL_DMA_STATE_BUSY != hdma->State) in HAL_DMA_PollForTransfer()
627 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; in HAL_DMA_PollForTransfer()
628 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
633 if ((hdma->Instance->CR & DMA_SxCR_CIRC) != RESET) in HAL_DMA_PollForTransfer()
635 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; in HAL_DMA_PollForTransfer()
643 mask_cpltlevel = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
648 mask_cpltlevel = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
651 regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_PollForTransfer()
654 while(((tmpisr & mask_cpltlevel) == RESET) && ((hdma->ErrorCode & HAL_DMA_ERROR_TE) == RESET)) in HAL_DMA_PollForTransfer()
662 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; in HAL_DMA_PollForTransfer()
665 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
668 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
677 if((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_PollForTransfer()
680 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_PollForTransfer()
683 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
686 if((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_PollForTransfer()
689 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_PollForTransfer()
692 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
695 if((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_PollForTransfer()
698 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_PollForTransfer()
701 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
705 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) in HAL_DMA_PollForTransfer()
707 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) in HAL_DMA_PollForTransfer()
709 HAL_DMA_Abort(hdma); in HAL_DMA_PollForTransfer()
712 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
715 hdma->State= HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
718 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
728 regs->IFCR = (DMA_FLAG_HTIF0_4 | DMA_FLAG_TCIF0_4) << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
730 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_PollForTransfer()
733 __HAL_UNLOCK(hdma); in HAL_DMA_PollForTransfer()
739 regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex; in HAL_DMA_PollForTransfer()
751 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) in HAL_DMA_IRQHandler() argument
758 DMA_Base_Registers *regs = (DMA_Base_Registers *)hdma->StreamBaseAddress; in HAL_DMA_IRQHandler()
763 if ((tmpisr & (DMA_FLAG_TEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
765 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET) in HAL_DMA_IRQHandler()
768 hdma->Instance->CR &= ~(DMA_IT_TE); in HAL_DMA_IRQHandler()
771 regs->IFCR = DMA_FLAG_TEIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
774 hdma->ErrorCode |= HAL_DMA_ERROR_TE; in HAL_DMA_IRQHandler()
778 if ((tmpisr & (DMA_FLAG_FEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
780 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_FE) != RESET) in HAL_DMA_IRQHandler()
783 regs->IFCR = DMA_FLAG_FEIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
786 hdma->ErrorCode |= HAL_DMA_ERROR_FE; in HAL_DMA_IRQHandler()
790 if ((tmpisr & (DMA_FLAG_DMEIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
792 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DME) != RESET) in HAL_DMA_IRQHandler()
795 regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
798 hdma->ErrorCode |= HAL_DMA_ERROR_DME; in HAL_DMA_IRQHandler()
802 if ((tmpisr & (DMA_FLAG_HTIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
804 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET) in HAL_DMA_IRQHandler()
807 regs->IFCR = DMA_FLAG_HTIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
810 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) in HAL_DMA_IRQHandler()
813 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) in HAL_DMA_IRQHandler()
815 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
818 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
824 if(hdma->XferM1HalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
827 hdma->XferM1HalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
834 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) in HAL_DMA_IRQHandler()
837 hdma->Instance->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
840 if(hdma->XferHalfCpltCallback != NULL) in HAL_DMA_IRQHandler()
843 hdma->XferHalfCpltCallback(hdma); in HAL_DMA_IRQHandler()
849 if ((tmpisr & (DMA_FLAG_TCIF0_4 << hdma->StreamIndex)) != RESET) in HAL_DMA_IRQHandler()
851 if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET) in HAL_DMA_IRQHandler()
854 regs->IFCR = DMA_FLAG_TCIF0_4 << hdma->StreamIndex; in HAL_DMA_IRQHandler()
856 if(HAL_DMA_STATE_ABORT == hdma->State) in HAL_DMA_IRQHandler()
859 hdma->Instance->CR &= ~(DMA_IT_TC | DMA_IT_TE | DMA_IT_DME); in HAL_DMA_IRQHandler()
860 hdma->Instance->FCR &= ~(DMA_IT_FE); in HAL_DMA_IRQHandler()
862 if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL)) in HAL_DMA_IRQHandler()
864 hdma->Instance->CR &= ~(DMA_IT_HT); in HAL_DMA_IRQHandler()
868 regs->IFCR = 0x3FU << hdma->StreamIndex; in HAL_DMA_IRQHandler()
871 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
874 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
876 if(hdma->XferAbortCallback != NULL) in HAL_DMA_IRQHandler()
878 hdma->XferAbortCallback(hdma); in HAL_DMA_IRQHandler()
883 if(((hdma->Instance->CR) & (uint32_t)(DMA_SxCR_DBM)) != RESET) in HAL_DMA_IRQHandler()
886 if((hdma->Instance->CR & DMA_SxCR_CT) == RESET) in HAL_DMA_IRQHandler()
888 if(hdma->XferM1CpltCallback != NULL) in HAL_DMA_IRQHandler()
891 hdma->XferM1CpltCallback(hdma); in HAL_DMA_IRQHandler()
897 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
900 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
907 if((hdma->Instance->CR & DMA_SxCR_CIRC) == RESET) in HAL_DMA_IRQHandler()
910 hdma->Instance->CR &= ~(DMA_IT_TC); in HAL_DMA_IRQHandler()
913 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
916 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
920 if(hdma->XferCpltCallback != NULL) in HAL_DMA_IRQHandler()
923 hdma->XferCpltCallback(hdma); in HAL_DMA_IRQHandler()
930 if(hdma->ErrorCode != HAL_DMA_ERROR_NONE) in HAL_DMA_IRQHandler()
932 if((hdma->ErrorCode & HAL_DMA_ERROR_TE) != RESET) in HAL_DMA_IRQHandler()
934 hdma->State = HAL_DMA_STATE_ABORT; in HAL_DMA_IRQHandler()
937 __HAL_DMA_DISABLE(hdma); in HAL_DMA_IRQHandler()
946 while((hdma->Instance->CR & DMA_SxCR_EN) != RESET); in HAL_DMA_IRQHandler()
949 hdma->State = HAL_DMA_STATE_READY; in HAL_DMA_IRQHandler()
952 __HAL_UNLOCK(hdma); in HAL_DMA_IRQHandler()
956 if(hdma->XferErrorCallback != NULL) in HAL_DMA_IRQHandler()
959 hdma->XferErrorCallback(hdma); in HAL_DMA_IRQHandler()
974 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Callb… in HAL_DMA_RegisterCallback() argument
980 __HAL_LOCK(hdma); in HAL_DMA_RegisterCallback()
982 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_RegisterCallback()
987 hdma->XferCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
991 hdma->XferHalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
995 hdma->XferM1CpltCallback = pCallback; in HAL_DMA_RegisterCallback()
999 hdma->XferM1HalfCpltCallback = pCallback; in HAL_DMA_RegisterCallback()
1003 hdma->XferErrorCallback = pCallback; in HAL_DMA_RegisterCallback()
1007 hdma->XferAbortCallback = pCallback; in HAL_DMA_RegisterCallback()
1023 __HAL_UNLOCK(hdma); in HAL_DMA_RegisterCallback()
1036 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef Cal… in HAL_DMA_UnRegisterCallback() argument
1041 __HAL_LOCK(hdma); in HAL_DMA_UnRegisterCallback()
1043 if(HAL_DMA_STATE_READY == hdma->State) in HAL_DMA_UnRegisterCallback()
1048 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1052 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1056 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1060 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1064 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1068 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1072 hdma->XferCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1073 hdma->XferHalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1074 hdma->XferM1CpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1075 hdma->XferM1HalfCpltCallback = NULL; in HAL_DMA_UnRegisterCallback()
1076 hdma->XferErrorCallback = NULL; in HAL_DMA_UnRegisterCallback()
1077 hdma->XferAbortCallback = NULL; in HAL_DMA_UnRegisterCallback()
1091 __HAL_UNLOCK(hdma); in HAL_DMA_UnRegisterCallback()
1121 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) in HAL_DMA_GetState() argument
1123 return hdma->State; in HAL_DMA_GetState()
1132 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) in HAL_DMA_GetError() argument
1134 return hdma->ErrorCode; in HAL_DMA_GetError()
1158 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32… in DMA_SetConfig() argument
1161 hdma->Instance->CR &= (uint32_t)(~DMA_SxCR_DBM); in DMA_SetConfig()
1164 hdma->Instance->NDTR = DataLength; in DMA_SetConfig()
1167 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) in DMA_SetConfig()
1170 hdma->Instance->PAR = DstAddress; in DMA_SetConfig()
1173 hdma->Instance->M0AR = SrcAddress; in DMA_SetConfig()
1179 hdma->Instance->PAR = SrcAddress; in DMA_SetConfig()
1182 hdma->Instance->M0AR = DstAddress; in DMA_SetConfig()
1192 static uint32_t DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma) in DMA_CalcBaseAndBitshift() argument
1194 uint32_t stream_number = (((uint32_t)hdma->Instance & 0xFFU) - 16U) / 24U; in DMA_CalcBaseAndBitshift()
1198 hdma->StreamIndex = flagBitshiftOffset[stream_number]; in DMA_CalcBaseAndBitshift()
1203 hdma->StreamBaseAddress = (((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)) + 4U); in DMA_CalcBaseAndBitshift()
1208 hdma->StreamBaseAddress = ((uint32_t)hdma->Instance & (uint32_t)(~0x3FFU)); in DMA_CalcBaseAndBitshift()
1211 return hdma->StreamBaseAddress; in DMA_CalcBaseAndBitshift()
1220 static HAL_StatusTypeDef DMA_CheckFifoParam(DMA_HandleTypeDef *hdma) in DMA_CheckFifoParam() argument
1223 uint32_t tmp = hdma->Init.FIFOThreshold; in DMA_CheckFifoParam()
1226 if(hdma->Init.MemDataAlignment == DMA_MDATAALIGN_BYTE) in DMA_CheckFifoParam()
1232 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1238 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1251 else if (hdma->Init.MemDataAlignment == DMA_MDATAALIGN_HALFWORD) in DMA_CheckFifoParam()
1260 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()
1266 if (hdma->Init.MemBurst == DMA_MBURST_INC16) in DMA_CheckFifoParam()
1287 if ((hdma->Init.MemBurst & DMA_SxCR_MBURST_1) == DMA_SxCR_MBURST_1) in DMA_CheckFifoParam()