Lines Matching refs:DCKCFGR2
2409 MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU)); in LL_RCC_SetUSARTClockSource()
2439 MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU)); in LL_RCC_SetUARTClockSource()
2467 MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U)); in LL_RCC_SetI2CClockSource()
2482 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource); in LL_RCC_SetLPTIMClockSource()
2522 MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U)); in LL_RCC_SetSDMMCClockSource()
2535 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource); in LL_RCC_SetCK48MClockSource()
2548 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource); in LL_RCC_SetRNGClockSource()
2561 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource); in LL_RCC_SetUSBClockSource()
2575 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source); in LL_RCC_SetCECClockSource()
2603 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source); in LL_RCC_SetDSIClockSource()
2666 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U)); in LL_RCC_GetUSARTClockSource()
2700 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U)); in LL_RCC_GetUARTClockSource()
2732 return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx); in LL_RCC_GetI2CClockSource()
2748 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)); in LL_RCC_GetLPTIMClockSource()
2792 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx); in LL_RCC_GetSDMMCClockSource()
2806 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx)); in LL_RCC_GetCK48MClockSource()
2820 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx)); in LL_RCC_GetRNGClockSource()
2834 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx)); in LL_RCC_GetUSBClockSource()
2849 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx)); in LL_RCC_GetCECClockSource()
2909 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx)); in LL_RCC_GetDSIClockSource()