34 #if defined(PWR)
166 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
173 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
205   SET_BIT(PWR->CR1, PWR_CR1_UDEN);  in LL_PWR_EnableUnderDriveMode()
215   CLEAR_BIT(PWR->CR1, PWR_CR1_UDEN);  in LL_PWR_DisableUnderDriveMode()
225   return (READ_BIT(PWR->CR1, PWR_CR1_UDEN) == (PWR_CR1_UDEN));  in LL_PWR_IsEnabledUnderDriveMode()
235   SET_BIT(PWR->CR1, PWR_CR1_ODSWEN);  in LL_PWR_EnableOverDriveSwitching()
245   CLEAR_BIT(PWR->CR1, PWR_CR1_ODSWEN);  in LL_PWR_DisableOverDriveSwitching()
255   return (READ_BIT(PWR->CR1, PWR_CR1_ODSWEN) == (PWR_CR1_ODSWEN));  in LL_PWR_IsEnabledOverDriveSwitching()
265   SET_BIT(PWR->CR1, PWR_CR1_ODEN);  in LL_PWR_EnableOverDriveMode()
275   CLEAR_BIT(PWR->CR1, PWR_CR1_ODEN);  in LL_PWR_DisableOverDriveMode()
285   return (READ_BIT(PWR->CR1, PWR_CR1_ODEN) == (PWR_CR1_ODEN));  in LL_PWR_IsEnabledOverDriveMode()
299   MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling);  in LL_PWR_SetRegulVoltageScaling()
312   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS));  in LL_PWR_GetRegulVoltageScaling()
322   SET_BIT(PWR->CR1, PWR_CR1_MRUDS);  in LL_PWR_EnableMainRegulatorDeepSleepUDMode()
332   CLEAR_BIT(PWR->CR1, PWR_CR1_MRUDS);  in LL_PWR_DisableMainRegulatorDeepSleepUDMode()
342   return (READ_BIT(PWR->CR1, PWR_CR1_MRUDS) == (PWR_CR1_MRUDS));  in LL_PWR_IsEnabledMainRegulatorDeepSleepUDMode()
352   SET_BIT(PWR->CR1, PWR_CR1_LPUDS);  in LL_PWR_EnableLowPowerRegulatorDeepSleepUDMode()
362   CLEAR_BIT(PWR->CR1, PWR_CR1_LPUDS);  in LL_PWR_DisableLowPowerRegulatorDeepSleepUDMode()
372   return (READ_BIT(PWR->CR1, PWR_CR1_LPUDS) == (PWR_CR1_LPUDS));  in LL_PWR_IsEnabledLowPowerRegulatorDeepSleepUDMode()
382   SET_BIT(PWR->CR1, PWR_CR1_FPDS);  in LL_PWR_EnableFlashPowerDown()
392   CLEAR_BIT(PWR->CR1, PWR_CR1_FPDS);  in LL_PWR_DisableFlashPowerDown()
402   return (READ_BIT(PWR->CR1, PWR_CR1_FPDS) == (PWR_CR1_FPDS));  in LL_PWR_IsEnabledFlashPowerDown()
412   SET_BIT(PWR->CR1, PWR_CR1_DBP);  in LL_PWR_EnableBkUpAccess()
422   CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);  in LL_PWR_DisableBkUpAccess()
432   return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP));  in LL_PWR_IsEnabledBkUpAccess()
447   SET_BIT(PWR->CSR1, PWR_CSR1_BRE);  in LL_PWR_EnableBkUpRegulator()
457   CLEAR_BIT(PWR->CSR1, PWR_CSR1_BRE);  in LL_PWR_DisableBkUpRegulator()
467   return (READ_BIT(PWR->CSR1, PWR_CSR1_BRE) == (PWR_CSR1_BRE));  in LL_PWR_IsEnabledBkUpRegulator()
480   MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);  in LL_PWR_SetRegulModeDS()
492   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));  in LL_PWR_GetRegulModeDS()
512 …MODIFY_REG(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS | PWR_CR1_MRUDS),…  in LL_PWR_SetPowerMode()
531 …return (uint32_t)(READ_BIT(PWR->CR1, (PWR_CR1_PDDS | PWR_CR1_LPDS | PWR_CR1_FPDS | PWR_CR1_LPUDS |…  in LL_PWR_GetPowerMode()
550   MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);  in LL_PWR_SetPVDLevel()
568   return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));  in LL_PWR_GetPVDLevel()
578   SET_BIT(PWR->CR1, PWR_CR1_PVDE);  in LL_PWR_EnablePVD()
588   CLEAR_BIT(PWR->CR1, PWR_CR1_PVDE);  in LL_PWR_DisablePVD()
598   return (READ_BIT(PWR->CR1, PWR_CR1_PVDE) == (PWR_CR1_PVDE));  in LL_PWR_IsEnabledPVD()
620   SET_BIT(PWR->CSR2, WakeUpPin);  in LL_PWR_EnableWakeUpPin()
642   CLEAR_BIT(PWR->CSR2, WakeUpPin);  in LL_PWR_DisableWakeUpPin()
664   return (READ_BIT(PWR->CSR2, WakeUpPin) == (WakeUpPin));  in LL_PWR_IsEnabledWakeUpPin()
686   SET_BIT(PWR->CR2, WakeUpPin);  in LL_PWR_SetWakeUpPinPolarityLow()
708   CLEAR_BIT(PWR->CR2, WakeUpPin);  in LL_PWR_SetWakeUpPinPolarityHigh()
730   return (READ_BIT(PWR->CR2, WakeUpPin) == (WakeUpPin));  in LL_PWR_IsWakeUpPinPolarityLow()
742   SET_BIT(PWR->CSR1, PWR_CSR1_EIWUP);  in LL_PWR_EnableInternalWakeUp()
752   CLEAR_BIT(PWR->CSR1, PWR_CSR1_EIWUP);  in LL_PWR_DisableInternalWakeUp()
762   return (READ_BIT(PWR->CSR1, PWR_CSR1_EIWUP) == (PWR_CSR1_EIWUP));  in LL_PWR_IsEnabledInternalWakeUp()
780   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF6) == (PWR_CSR2_WUPF6));  in LL_PWR_IsActiveFlag_WU6()
790   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF5) == (PWR_CSR2_WUPF5));  in LL_PWR_IsActiveFlag_WU5()
800   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF4) == (PWR_CSR2_WUPF4));  in LL_PWR_IsActiveFlag_WU4()
810   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF3) == (PWR_CSR2_WUPF3));  in LL_PWR_IsActiveFlag_WU3()
820   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF2) == (PWR_CSR2_WUPF2));  in LL_PWR_IsActiveFlag_WU2()
830   return (READ_BIT(PWR->CSR2, PWR_CSR2_WUPF1) == (PWR_CSR2_WUPF1));  in LL_PWR_IsActiveFlag_WU1()
840   return (READ_BIT(PWR->CSR1, PWR_CSR1_SBF) == (PWR_CSR1_SBF));  in LL_PWR_IsActiveFlag_SB()
850   return (READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO));  in LL_PWR_IsActiveFlag_PVDO()
860   return (READ_BIT(PWR->CSR1, PWR_CSR1_BRR) == (PWR_CSR1_BRR));  in LL_PWR_IsActiveFlag_BRR()
870   return (READ_BIT(PWR->CSR1, PWR_CSR1_VOSRDY) == (PWR_CSR1_VOSRDY));  in LL_PWR_IsActiveFlag_VOS()
880   return (READ_BIT(PWR->CSR1, PWR_CSR1_ODRDY) == (PWR_CSR1_ODRDY));  in LL_PWR_IsActiveFlag_OD()
890   return (READ_BIT(PWR->CSR1, PWR_CSR1_ODSWRDY) == (PWR_CSR1_ODSWRDY));  in LL_PWR_IsActiveFlag_ODSW()
900   return (READ_BIT(PWR->CSR1, PWR_CSR1_UDRDY) == (PWR_CSR1_UDRDY));  in LL_PWR_IsActiveFlag_UD()
910   SET_BIT(PWR->CR1, PWR_CR1_CSBF);  in LL_PWR_ClearFlag_SB()
920   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF6);  in LL_PWR_ClearFlag_WU6()
930   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF5);  in LL_PWR_ClearFlag_WU5()
940   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF4);  in LL_PWR_ClearFlag_WU4()
950   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF3);  in LL_PWR_ClearFlag_WU3()
960   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF2);  in LL_PWR_ClearFlag_WU2()
970   WRITE_REG(PWR->CR2, PWR_CR2_CWUPF1);  in LL_PWR_ClearFlag_WU1()
980   WRITE_REG(PWR->CSR1, PWR_CSR1_UDRDY);  in LL_PWR_ClearFlag_UD()